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DTSTART;VALUE=DATE:20260831
DTEND;VALUE=DATE:20260905
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SUMMARY:SEMICON Taiwan 2026
DESCRIPTION:SEMICON Taiwan is not just a platform that connects Taiwan and global microelectronics ecosystems but also a bridge that facilitates smooth collaboration between the industry\, the government\, academia\, and research institutions. Witnessing enormous business collaboration\, SEMICON Taiwan still stays true to its missions― Leading Technology Trends\, Driving Technology Innovation\, and Facilitating Collaboration and continues providing various channels and activities that meet the companies’ marketing and promotion needs. \nREGISTER HERE
URL:https://semiwiki.com/event/semicon-taiwan-2026/
LOCATION:TaiNEX\, TaiNEX\, No.1\, Jingmao 2nd Rd.\, Taipei City\, Nangang District\, 11568\, Taiwan
ATTACH;FMTTYPE=image/jpeg:https://semiwiki.com/wp-content/uploads/2026/06/top.jpg
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DTSTART;VALUE=DATE:20260901
DTEND;VALUE=DATE:20260904
DTSTAMP:20260804T014240Z
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SUMMARY:DVCon India 2026
DESCRIPTION:The premier conference on the application of languages\, tools\, methodologies and standards for the design and verification of electronic systems and integrated circuits. \nDear Design\, Verification and Validation Community\, \nIt is my great pleasure to welcome you to DVCon India 2026\, taking place September 1-3\, 2026\, at Radisson Blu (Marathahalli) in Bengaluru\, the vibrant hub of India’s semiconductor and design innovation ecosystem. As General Chair\, I am thrilled to invite you to join us for what promises to be our most expansive event yet. Building on the success of previous DVCon editions\, we are excited to extend the program to three full days—inspired by the robust agendas of previous years. This allows even more time for papers\, discussions and deep dives into cutting-edge topics in design and verification\, including AI-driven methodologies\, system-level design\, hardware-software co-verification\, and emerging standards.We are in the final stages of securing IEEE technical sponsorship\, underscoring the conference’s commitment to high-quality\, peer-reviewed technical content that advances our industry.DVCon India 2026 is your platform to connect\, collaborate\, and contribute. \nWe warmly invite you to: \n\nSubmit papers\, posters\, tutorials\, or workshops—share your innovations and shape the agenda (calls opening soon!).\nExhibit or sponsor—gain visibility among key industry leaders.\nAttend as an audience member—network\, learn\, and stay ahead of the curve.\n\nWhether you’re a seasoned expert or emerging talent\, your participation will make this event unforgettable. Mark your calendars\, and let’s drive the future of design and verification together! \n\n\nShreya Dasgupta\nAnalog Devices\nGeneral Chair\, DVCon India 2026 \n\nREGISTER HERE
URL:https://semiwiki.com/event/dvcon-india-2026/
LOCATION:Radisson Blu Bengaluru\, Radisson Blu Bengaluru\, Bangalore\, India
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DTSTART;VALUE=DATE:20260902
DTEND;VALUE=DATE:20260903
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SUMMARY:GlobalFoundries Technology Summit 2026 North America
DESCRIPTION:About GTS\n\nHosted across the globe\, GTS is GlobalFoundries’ annual flagship event\, where GF and industry leaders\, technologists\, customers and partners explore how disruptive technologies are shaping intelligent systems and the semiconductor industry as a whole. Each GTS event includes deep dives into the impact of GF’s differentiated solutions\, results and innovations from our customers and end-to-end partner ecosystem across our proven process technologies. \n\nGTS highlights\n\n\nHear from our business leaders – Explore how GF’s purpose-built technologies are shaping pivotal innovations\nExperience immersive keynotes – Attend engaging keynotes from industry-leaders that shed light on industry trends and developments achieved in partnership with GF\nNetwork with our partners across the globe – Connect with our GlobalSolutions™ ecosystem and value-added partners in our partner pavilion and networking events\nEngage with GF technical experts – Dive into immersive technical deep dives with our technologists and partners that showcase upcoming roadmap innovations leveraging GF process technologies\n\nREGISTER HERE
URL:https://semiwiki.com/event/globalfoundries-technology-summit-2026-north-america/
LOCATION:Santa Clara\, CA\, Santa Clara\, CA\, United States
ATTACH;FMTTYPE=image/webp:https://semiwiki.com/wp-content/uploads/2026/08/B800-FWEBP.webp
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DTSTART;TZID=America/Los_Angeles:20260902T090000
DTEND;TZID=America/Los_Angeles:20260902T100000
DTSTAMP:20260819T035232Z
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SUMMARY:Webinar: High-Level Synthesis Summer Hackathon: From Python to High-Performance AI Accelerators
DESCRIPTION:Designing AI inference hardware for edge applications often requires building custom hardware accelerated solutions to meet the demands for ultra-low power consumption and strict real-time response requirements. This webinar introduces Catapult™ AI NN\, which provides an automated flow that starts with a Python neural network model and generates an RTL hardware accelerator. The flow enables rapid exploration of design alternatives\, helping teams identify the right implementation that best meets their Power\, Performance\, and Area goals. \nYou can go beyond just hearing about the technology and put it to work yourself. Join our High-Level Synthesis Summer Hackathon for a hands-on experience building an AI accelerator. Participants will use Catapult AI NN to create the RTL for an AI “Roadside Recognizer\,” integrate it into a RISC-V based RTL processor design\, verify the complete system\, and measure the accelerator’s Power\, Performance\, and Area. \nThe winning team will be the one that meets the required performance\, accuracy\, and area constraints while achieving the lowest energy per inference. Winners will take home valuable prizes and\, of course\, the glory that comes with building the most energy-efficient design! \nWhat you will learn: \n\n\nHow to create an RTL hardware accelerator from a Python/ Keras neural network model using Catapult AI NN.\nHow to optimize the accelerator implementation through parallelization\, pipelining\, and resource sharing.\nHow to explore architectural alternatives to achieve your PPA goals\nHow to target your design to either FPGA or ASIC.\nHow to integrate your hardware accelerator into a RISC-V processing sub-system.\n\n\nWho should attend: \n\n\nHardware designers developing inferencing systems for edge or ultra low-power solutions.\nSystem architects exploring trade-offs between hardware performance\, power\, area\, and cost.\nProject owners looking to accelerate their hardware design process.\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/webinar-high-level-synthesis-summer-hackathon-from-python-to-high-performance-ai-accelerators/
LOCATION:Online
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