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DTSTART;VALUE=DATE:20260804
DTEND;VALUE=DATE:20260806
DTSTAMP:20260211T220912Z
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SUMMARY:Realize LIVE Asia-Pacific 2026
DESCRIPTION:Where your digital transformation gets real — fast\nWe are excited to be visiting a new city with the Realize LIVE digital transformation conference to showcase artifial intelligence\, digitalization\, sustainability and optimization across the product lifecycle. Learn\, network and connect with the Siemens software community\, and walk away with new tools and insights for your digital journey. \nGet a sneak peek of what you can expect! \n\n\n\n\nAccelerate your digital transformation journey\n\n\n\n\n\n\n\nBecome a better user\nLeave empowered — 85% of Realize LIVE event attendees leave with new skills and enhanced tool proficiency. \n\n\nBecome inspired by thought leaders\nRealize LIVE participants become inspired after attending sessions led by customers and Siemens experts\, who share real-world insights and innovations\, leave event participants inspired. \n\n\nStay ahead with product roadmaps\nStay up-to-date with exclusive product presentations showcasing the latest advancements in Siemens technology\, and preview upcoming updates to plan for what’s next. \n\n\nGain exclusive access to training and certification\nGet 60 days of access to Siemens Xcelerator Academy\, as well as a voucher to Siemens Xcelerator Certification (valid for six months). \n\n\nConnect and celebrate with product experts\nJoin the Realize LIVE reception and dedicated meet-ups to connect with peers who are on their digital transformation journey. \n\n\nDive into the Siemens ecosystem\nRealize LIVE is your destination for all things related to digital transformation. Meet experts; engage with partners; and experience live demos in the solutions center. \n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/realize-live-asia-pacific-2026/
LOCATION:Bengaluru\, India\, Bengaluru\, India
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/02/Screenshot-2026-02-11-140843.png
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DTSTART;VALUE=DATE:20260804
DTEND;VALUE=DATE:20260807
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UID:370361-1785801600-1786060799@semiwiki.com
SUMMARY:Future of Memory and Storage (FMS) 2026: 20th Anniversary
DESCRIPTION:What is FMS?\nOur over-arching mission is to help accelerate the move towards a world where advanced memory and storage technologies enable AI systems\, data centers\, hyperscalers and enterprises to operate at unprecedented scale\, speed and efficiency. All the while supporting the engineers and architects building the infrastructure of the future. \nFUTURE OF MEMORY & STORAGE is a multi-faceted event experience providing the most comprehensive and technically credible memory and storage event on the planet. It is carefully curated by an experienced team plugged into a global network. \nOur presenters are visionary industry leaders\, engineers and architects from all disciplines. They are selected for their relevance\, dynamism and insight. \nREGISTER HERE
URL:https://semiwiki.com/event/future-of-memory-and-storage-fms-2026-20th-anniversary/
LOCATION:Santa Clara Convention Center\, Santa Clara Convention Center\, 5001 Great America Pkwy\, Santa Clara\, CA\, United States
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/06/Screenshot-2026-06-16-134008.png
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DTSTART;TZID=America/Los_Angeles:20260804T090000
DTEND;TZID=America/Los_Angeles:20260804T100000
DTSTAMP:20260714T012229Z
CREATED:20260714T012229Z
LAST-MODIFIED:20260714T012229Z
UID:371202-1785834000-1785837600@semiwiki.com
SUMMARY:Webinar: Enabling Agile CI/CD in Chip Design: Running Synopsys EDA Flows from GitHub
DESCRIPTION:Featured Speakers: \n\nAchim Nohl\, Distinguished Architect\, Synopsys\nVarun Shah\, Product Management Director\, Synopsys\n\nHardware teams are moving to GitHub\, CI/CD\, and Pull Request-driven workflows\, but EDA tools often sit outside that loop – breaking collaboration and slowing agentic automation. \nThis Synopsys webinar demonstrates how Synopsys Cloud GitHub Apps bring chip design and verification flows directly into GitHub events such as pull requests\, pushes\, and slash commands. \nSee how EDA runs as ephemeral cloud workloads with results posted back as PR checks and comments\, enabling continuous verification without leaving GitHub. We’ll also cover security models for IP-sensitive environments and how GitHub-native EDA unlocks agent-driven workflows where AI can trigger\, interpret\, and act on design tool results – closing the gap between software-style hardware development and traditional EDA execution. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nFeatured Speakers\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nAchim Nohl \nDistinguished Architect\, Synopsys \nAchim Nohl is a Distinguished Architect at Synopsys\, where he co-architects and develops the Synopsys Cloud platform. With over 25 years of experience spanning EDA\, embedded systems\, and cloud-native architecture\, his career has evolved from processor design and prototyping all the way to SaaS platform development. He holds multiple patents in Embedded Processor Design Automation\, was part of the founding team of LISATek in 2000. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nVarun Shah \nDirector\, Synopsys \nVarun Shah is on the product management team of Synopsys Cloud\, responsible for technology roadmap and cloud enablement of EDA software. Prior to joining the cloud team\, Varun was in Application Engineering for design verification software for over a decade. Varun holds a master’s degree in electrical engineering and is a certified product management professional from the Kellogg School of Management. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/webinar-enabling-agile-ci-cd-in-chip-design-running-synopsys-eda-flows-from-github/
LOCATION:Online
ATTACH;FMTTYPE=image/jpeg:https://semiwiki.com/wp-content/uploads/2026/07/Synopsys-400x400-px-High-Quality-1.jpg
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DTSTART;TZID=America/Los_Angeles:20260804T130000
DTEND;TZID=America/Los_Angeles:20260804T140000
DTSTAMP:20260717T011926Z
CREATED:20260717T011926Z
LAST-MODIFIED:20260717T011926Z
UID:371347-1785848400-1785852000@semiwiki.com
SUMMARY:Webinar: Compensating for PCB laminate anisotropy in SI calculations
DESCRIPTION:Why Your Impedance Models May Be Less Accurate Than You Think\nFor many years\, the PCB industry has accepted dielectric values without fully understanding how they were measured—or whether they’re the right values for impedance modeling. This webinar explores what that means for today’s high-speed designs. \nAs signaling speeds continue to increase\, even small errors in dielectric modeling can translate into measurable impedance errors\, degraded simulation correlation\, and reduced design margins. Most PCB design teams rely on laminate data supplied by material vendors and fabricators—but few engineers understand how those dielectric values were measured\, what they actually represent\, or whether they’re appropriate for impedance modeling. In this webinar\, Bill Hargin\, founder of Z-zero and developer of Z-planner Enterprise\, explains why dielectric measurement orientation matters\, how laminate anisotropy affects transmission-line modeling\, and what design teams can do to improve impedance prediction accuracy. Drawing on extensive research across hundreds of laminate materials and nearly thirty dielectric characterization methods\, Bill explains why many published Dk values are not directly applicable to signal-integrity analysis—and why understanding the difference between Dk(x-y) and Dk(z) is becoming increasingly important for today’s high-speed designs. \nWhat You’ll Learn\n\nWhy many published laminate Dk values introduce impedance error\nThe difference between Dk(x-y) and Dk(z)—and why it matters\nHow dielectric measurement methods influence laminate datasheets\nWhy resin content\, glass style\, copper roughness\, and frequency affect impedance\nPractical techniques for improving simulation accuracy and fabrication correlation\nHow next-generation impedance planning tools address these challenges\n\nWho Should Attend\n\nHardware Design Engineers\nSignal Integrity Engineers\nPCB Designers\nPCB Fabricators\nCAD and Library Engineers\nHigh-speed digital design teams\nAnyone responsible for PCB stackup planning or impedance control\n\nWhy Attend?\nIf you’ve ever wondered why simulated impedance doesn’t always match fabricated hardware—or whether the dielectric numbers in your stackups tell the whole story—this webinar will provide practical answers backed by research\, engineering data\, and real-world examples. Whether you’re designing 56G\, 112G\, 224G\, or simply trying to build more predictable hardware\, you’ll leave with a better understanding of the physics behind modern PCB impedance planning. Reserve your seat today. \nREGISTER HERE
URL:https://semiwiki.com/event/webinar-compensating-for-pcb-laminate-anisotropy-in-si-calculations/
LOCATION:Online
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