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DTSTART;VALUE=DATE:20260518
DTEND;VALUE=DATE:20260521
DTSTAMP:20260509T052915
CREATED:20250828T060208Z
LAST-MODIFIED:20250828T060208Z
UID:361093-1779062400-1779321599@semiwiki.com
SUMMARY:VOICE 2026
DESCRIPTION:VOICE is a developer conference\, created by test engineers for test engineers.\n\n\n\n\n\n\n\n\nEach year\, the VOICE Developer Conference unites semiconductor test professionals representing the world’s leading integrated device manufacturers (IDMs)\, foundries\, fabless semiconductor companies and outsourced semiconductor assembly and test (OSAT) providers to exchange information about the latest technology advancements\, express new ideas\, share best practices and network with one another. \n\n\n\n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/voice-2026/
LOCATION:Scottsdale\, Arizona\, Scottsdale\, AZ\, United States
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2025/08/Screenshot-2025-08-27-230026.png
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DTSTART;VALUE=DATE:20260518
DTEND;VALUE=DATE:20260521
DTSTAMP:20260509T052915
CREATED:20260414T061153Z
LAST-MODIFIED:20260414T061153Z
UID:368387-1779062400-1779321599@semiwiki.com
SUMMARY:Surface Preparation and Cleaning Conference (SPCC)
DESCRIPTION:Surface Preparation and Cleaning Conference (SPCC)\, formerly presented by Linx Consulting\, brings together key business insights\, IC manufacturers\, equipment makers\, materials and chemical providers\, metrology experts\, process technologists to address critical challenges\, and innovations in surface preparation and cleaning. \nHeld at the Wild Horse Pass Resort in Chandler\, Arizona\, SPCC 2026 will feature technical sessions\, poster presentations\, and business-focused programming\, creating a unique forum where technology and industry strategy converge. \nREGISTER HERE
URL:https://semiwiki.com/event/surface-preparation-and-cleaning-conference-spcc/
LOCATION:Wild Horse Pass\, Wild Horse Pass\, 5040 Wild Horse Pass Blvd\, Chandler\, AZ\, 85226\, United States
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/04/Screenshot-2026-04-13-231044.png
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DTSTART;VALUE=DATE:20260519
DTEND;VALUE=DATE:20260520
DTSTAMP:20260509T052915
CREATED:20260414T060148Z
LAST-MODIFIED:20260414T060148Z
UID:368372-1779148800-1779235199@semiwiki.com
SUMMARY:CadenceCONNECT: Tech Days Europe 2026 - Cambridge
DESCRIPTION:Join us at CadenceCONNECT: Tech Days Europe 2026\, our annual\, free\, multi-track event dedicated to the engineers\, innovators\, and visionaries shaping the future of electronic design. Our aim is to bring together like minded thinkers to explore how AI-driven Cadence technologies are transforming design workflows\, boosting productivity\, and enabling breakthroughs across every domain. \nEvent Details\n06 May 2026 – 30 Jun 2026 \nVarious \nREGISTER HERE
URL:https://semiwiki.com/event/cadenceconnect-tech-days-europe-2026-cambridge/
LOCATION:Cambridge\, UK\, Cambridge\, England\, United Kingdom
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DTSTART;TZID=America/Los_Angeles:20260519T090000
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DTSTAMP:20260509T052915
CREATED:20260505T081403Z
LAST-MODIFIED:20260505T081403Z
UID:369064-1779181200-1779184800@semiwiki.com
SUMMARY:Webinar: Intel: From Construction to Signoff: 3DIC Methodology for Disaggregated Designs
DESCRIPTION:Featured Speaker: \n\nVictoria Kolesov\, Principal Engineer\, Intel\n\nIn this Synopsys webinar\, Intel will present how its disaggregated designs across client and server platforms have driven the evolution of robust 3D multi-die design construction and signoff methodologies. Intel will share practical experience using Synopsys’ complete design implementation and signoff flows for static timing analysis signoff and 3D layout verification in both passive and active interposer designs. The session highlights how increasing accuracy requirements have shaped 3D construction practices\, standards\, and collateral\, enabling consistent\, correct‑by‑construction signoff across process nodes\, TSVs\, and complex die‑to‑die interconnects. \nWhat you’ll learn: \n\nHow Intel approaches 3DIC construction for disaggregated designs\nKey requirements for static timing and layout signoff in 3DIC flows\nDifferences between passive and active interposer signoff considerations\nHow accuracy requirements influence 3D construction methodologies\nBest practices for achieving correct‑by‑construction 3DIC signoff\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nFeatured Speaker\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nVictoria Kolesov \nPrincipal Engineer\, Intel \nVictoria Kolesov joined Intel in 2001 and has held a variety of responsibilities including RTL development\, design completion\, and design automation. Her current focus is interconnect implementation and 3D design integration. Victoria obtained her MS in Computer Science from St.Petersburg Technical University\, Russia. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/webinar-intel-from-construction-to-signoff-3dic-methodology-for-disaggregated-designs/
LOCATION:Online
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