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DTSTART;VALUE=DATE:20260426
DTEND;VALUE=DATE:20260502
DTSTAMP:20260419T193856
CREATED:20260107T101053Z
LAST-MODIFIED:20260107T101053Z
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SUMMARY:2026 MRS Spring Meeting & Exhibit
DESCRIPTION:The 2026 MRS Spring Meeting & Exhibit\, taking place April 26–May 1 in Honolulu\, Hawai‘i\, will convene materials researchers from academia\, industry\, government and national laboratories together for a week of cross-disciplinary collaboration and scientific exchange. Set against the backdrop of one of MRS’s most inspiring locations\, the Meeting & Exhibit will feature breakthroughs in areas such as sustainable manufacturing\, advanced characterization and energy materials—driving forward innovation on a global scale. \nBuilding on this inspiring setting\, the Meeting will span four official venues in Honolulu. Technical programming\, events and accommodations will be distributed within the city’s walkable\, picturesque layout\, creating a dynamic\, interconnected format that will support active engagement and collaboration while maintaining a focused environment for research and application dialogue throughout the Meeting week. \nWhether you’re looking to present new research\, explore emerging technologies\, or engage with peers across disciplines\, the 2026 MRS Spring Meeting will provide an unforgettable experience in an extraordinary location. \nREGISTER HERE
URL:https://semiwiki.com/event/2026-mrs-spring-meeting-exhibit/
LOCATION:Honolulu\, Hawaii\, Honolulu\, HI\, United States
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DTSTART;VALUE=DATE:20260429
DTEND;VALUE=DATE:20260501
DTSTAMP:20260419T193856
CREATED:20260107T101637Z
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SUMMARY:SEMIEXPO Heartland
DESCRIPTION:FOCUSED ON SMART MANUFACTURING & SMART MOBILITY\n\n\nDRIVING SEMICONDUCTOR BUSINESS IN THE MIDWEST \nThank you for being part of the launch of SEMIEXPO Heartland—where Smart Manufacturing and Smart Mobility came together like never before! This groundbreaking event opened new opportunities for collaboration and growth\, driving us toward the semiconductor industry’s $1T future. \nWith so much innovation concentrated in the Midwest\, SEMIEXPO Heartland is just getting started. Stay tuned for our next chapter in Spring 2026—we’ll see you in Detroit\, MI! Get ready for even more inspiration\, insights\, and connections at the intersection of two critical markets. \nMAKE AN IMPACT AT THE INAUGURAL SEMIEXPO HEARTLAND \nPlan Now to Exhibit or Sponsor. Contact—\nShane Poblete | +1 202-847-5983 | spoblete@semi.org \n\n\n\n\n2025 Post Show Report\n\n\n\n\n\n\n\nAnalytics & Statistics\nAttendee Demographics\nKeynotes\nProgram Highlights\nAnd more!\n\n\n\n\n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/semiexpo-heartland/
LOCATION:Detroit Marriott at the Renaissance Center\, 400 Renaissance Dr W\, Detroit\, MI\, 48243\, United States
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DTSTART;TZID=America/Los_Angeles:20260429T070000
DTEND;TZID=America/Los_Angeles:20260429T080000
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CREATED:20260414T051207Z
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SUMMARY:Webinar: Application-Specific Processors (ASIPs) for Physical AI
DESCRIPTION:Physical AI is increasingly popular in applications requiring real-time decision making and autonomous operation.  Different from NPUs for cloud platforms\, Physical AI processors can be made application-specific.  By jointly tuning their ISA and memory architecture to the network models required by the application\, power consumption and silicon area are drastically reduced. \nSynopsys ASIP Designer is the industry-leading tool to explore\, design\, and optimize application-specific instruction-set processors (ASIPs)\, including custom NPUs for physical AI. \nIn this Synopsys webinar\, we present the design of “SmarT”\, an ASIP with a RISC-V ISA augmented with specialized vector units for convolutions and quantization\, with 64 MACs. It supports circular gather/scatter addressing of vector data in parallel with computations. Low-overhead DMA moves data blocks from external to local memory. \nNext\, we present a multi-core RISC-V based accelerator for hyperdimensional computing\, designed with ASIP Designer by TU Munich. It applies near-memory computing (NMC) to minimize power consumption and memory bandwidth. This 5-core chip is the first university-led tape-out in Germany using TSMC 7nm technology. \nLearn about: \n\nSynopsys ASIP Designer\, the industry-leading tool to explore\, design and optimize application specific processors\nASIP Design methodologies to address challenges in jointly optimizing the memory architecture and the computational resources for Physical AI architectures\nTwo ASIP designs examples with customize memory architectures for Physical AI applications\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nFeatured Speaker\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nDr. Falco Munsche \nTechnical Product Marketing\, Synopsys \nFalco Munsche is the Technical Product Manager for ASIP design tools at Synopsys. Previously he worked for a total of 20 years as Application Engineer and Software Engineer of ASIP design tools for Synopsys and CoWare\, and as a Design Consultant for Synopsys. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nProf. Hussam Amrouch \nTechnical University of Munich\, Germany \nHussam Amrouch is Professor heading the Chair of AI Processor Design within the Technical University of Munich (TUM). He is the head of Brain-inspired Computing at the Munich Institute of Robotics. Further\, he is the head of the Semiconductor Test and Reliability at the University of Stuttgart. He is the Academic Director of TUM Venture Labs. He is Founding Director of the Munich Advanced-Technology Center for AI Chips (MACHT-AI). \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/webinar-application-specific-processors-asips-for-physical-ai/
LOCATION:Online
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