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Webinar: Using High-Level Synthesis to Accelerate Computer/Machine Vision Applications
October 1 @ 10:00 am - 11:00 am
HLS has been used in multiple companies, projects, and designs targeting vision processing for the past several years. HLS adoption continues to grow because it is the fastest way to turn complex algorithms into efficient hardware implementations. HLS creates a methodology that enables design teams to rapidly react to changes in algorithm or functional specifications while still meeting demanding schedules. This webinar steps through the basics of how HLS works and why it is such a good fit for image processing and vision applications, using a practical example vision algorithm.
This webinar is part 2 of the webinar series “HLS for Vision and Deep Learning Hardware Accelerators”
What You Will Learn
- How HLS is used to implement a computer vision algorithm in either an FPGA or ASIC technology and the trade-offs for power and performance.
- How HLS is employed to analyze unique architectures for a very energy-efficient inference solution such as a CNN (Convolutional Neural Network) from a pre-trained network.
- How to integrate the design created in HLS into a larger system, including peripherals, processor, and software.
- How to verify the design in the context of the larger system and how to deploy it into an FPGA prototype board.
Who Should Attend
- RTL Designers or Project Managers interested in moving up to HLS to improve design and verification productivity.
- Architects or hardware-aware algorithm developers in the field of image processing, computer vision, machine and deep learning, that are interested in rapid and accurate exploration of power/performance metrics.
- New project teams with only a few hardware designers and multiple software experts that want to rapidly create high-performance FPGA or ASIC IP for computer vision or deep learning markets.