Webinar: Minimize Layout Iterations and EM Errors with Simulation-Driven Routing

Overview

Electromigration (EM) has a major impact on IC reliability and lifespan. Long a concern for automotive, aerospace, and healthcare, EM is now a challenge for the entire microelectronics industry as we move to lower process nodes.

To address this concern, Cadence built upon its electrically aware design (EAD) technology to create, simulation-driven routing (SDR). SDR provides immediate EM and parasitic feedback to engineers creating layout geometries to connect components.

Featuring a unique in-design solution, interactive SDR provides a powerful new way to meet current density constraints with a predictable flow. By using simulation information derived earlier in the design cycle, ECOs that occur due to EM violations can be eliminated. In turn, it improves layout productivity by up to 50% through significantly reducing signoff time, decreasing design iterations, and increasing reliability.

In this one-hour webinar and demonstration, learn:

• How SDR works in parallel with EAD to ensure the design meets all EM current density requirements
• How simulation-derived information earlier in the design cycle can eliminate the ECOs that occur due to EM violations
• The benefits of the Virtuoso® Layout Suite’s tight integration with the Spectre® Simulation Platform and Virtuoso ADE Product Suite

Date and Times

Wednesday, June 3

Please select the time that suits best with your schedule

Option 1 (EMEA and India): 9:00 BST, 10:00 CEST, 11:00 EEST, 13:30 IST

Option 2 (North America): 11:00AM PDT, 1:00PM CDT, 2:00PM EDT