Webinar: Introduction to Logic Simulator Programming Interfaces for FPGA Designs (Three Part Webinar Series) Part 2: The Power of VHDL’s VHPI (US)

Abstract:

The programming interfaces of logic simulators are largely the domain of specialists writing proprietary tools and extensions and are only vaguely in the consciousness of many design and verification engineers, if aware at all. Yet the simplest use of such interfaces opens up a whole world of possibilities in extending what is achievable in verifying logic IP and with the potential for logic and embedded software co-development.

Agenda:

• Introduction 
• VHDL VHPI
• OSVVM co-simulation VHPI interface
• OSVVM co-simulation environment
• Demo of RISC-V software ISS running in logic simulation
• Demo of external program connected via TCP/IP socket
• Conclusions
• Q&A

Webinar Duration

• 45 min presentation/live demo
• 15 min Q&A

Presenter Bio:

Simon Southwell has 35 years in Research and Development, with experience in ASIC design, FPGA, and embedded software development. Now spending time contributing IP to the open-source community, and sharing experience and knowledge through writing articles and mentoring undergraduates and junior engineers. Also currently a collaborator on the OSVVM project, a verification methodology and VHDL library, adding and supporting its co-simulation capabilities. Particular areas of interest include processor systems and sub-systems, system modelling in software, the software/hardware interface and co-simulation of logic and software.