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Webinar: Implementing Machine Learning Hardware Using High-Level Synthesis
October 8 @ 10:00 am - 11:00 am
Neural networks are typically developed and trained in a high-performance 32-bit floating-point compute environment. But, in many cases a custom hardware solution is needed for the inference engine to meet power and real-time requirements. Each neural network and end-application may have different performance requirements that can dictate the optimal hardware architecture. This makes custom-tailored solutions impossible when using hand-coded RTL creation flows. HLS has the unique ability to quickly go from complex algorithms written in C to generated RTL, enabling accurate profiles for power and performance for an algorithm’s implementation without having to write it by hand. This webinar steps through a CNN (Convolutional Neural Network) inference engine implementation, highlighting specific architectural choices, and shows how to integrate and test inside of TensorFlow. This demonstrates how an HLS flow is used to rapidly design custom CNN accelerators.
This webinar is part 3 of the webinar series “HLS for Vision and Deep Learning Hardware Accelerators”
What You Will Learn
- How HLS is used to implement a computer vision algorithm in either an FPGA or ASIC technology and the trade-offs for power and performance.
- How HLS is employed to analyze unique architectures for a very energy-efficient inference solution such as a CNN (Convolutional Neural Network) from a pre-trained network.
- How to integrate the design created in HLS into a larger system, including peripherals, processor, and software.
- How to verify the design in the context of the larger system and how to deploy it into an FPGA prototype board.
Who Should Attend
- RTL Designers or Project Managers interested in moving up to HLS to improve design and verification productivity.
- Architects or hardware-aware algorithm developers in the field of image processing, computer vision, machine and deep learning, that are interested in rapid and accurate exploration of power/performance metrics.
- New project teams with only a few hardware designers and multiple software experts that want to rapidly create high-performance FPGA or ASIC IP for computer vision or deep learning markets.