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Webinar: Imperas RISC-V simulation technology with eSol Trinity and NSITEXE
Imperas RISC-V reference models highlighted for software development and RISC-V processor verification, including an example project with NSITEXE.
Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced with eSol Trinity the webinar event on RISC-V reference models and simulation technology for the growing adoption of RISC-V in Japan. This webinar will feature a guest speaker – Mr. Marume of NSITEXE Co., Ltd., a group company of the DENSO Corporation that develops and sells high-performance semiconductor IPs, will introduce an example of using the Imperas RISC-V reference model and simulator.
RISC-V is an open ISA (Instruction Set Architecture), which permits many configurations and options for processor implementation and microarchitectural features. The vector instruction extensions support complex arithmetic operations required for applications involving linear algebra, such as AI (Artificial Intelligence) and ML (Machine Learning). Extensive test and verification is required to achieve the Automotive industry standard ASIL D safety requirement level of the ISO 26262 functional safety standard for vehicles.
Virtual Platforms based on Imperas models and simulator allow early SoC architectural exploration as system developers map complex AI algorithms to new multiprocessor configurations. As RISC-V supports both standard instruction extensions such as vectors, as well as user defined custom instructions, the Imperas models and analysis tools support the complete flexibility and design freedoms for the front-end design flow. As the project develops to the next phase, the hardware design verification (DV) team can use the Imperas RISC-V reference model and verification suite to validate the design before tape-out. Due to the broad range of configurations available for the vector extensions the Imperas verification suite includes a compliance validation test to ensure early software compatibility with the growing ecosystem supporting RISC-V vector extensions.
Webinar: ‘Imperas RISC-V reference model and high speed simulation technology’
When: March 30th 2022
Where: 2:00-2:30pm (JST) Live streaming (Zoom)
For more information including registration please visit this link.
For more information about Imperas, please see www.imperas.com. Follow Imperas on LinkedIn, twitter @ImperasSoftware and YouTube.
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