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Webinar: HLS — What, How and Why Now?
September 24, 2019 @ 10:00 AM - 11:00 AM
HLS has been around for years, so why are we seeing such growth now? This webinar starts with an introduction of basic HLS concepts, design methodologies, best fits for HLS with customer use cases/highlights that explain the benefits they experienced and their adoption path. It will then move to a discussion of trends and an introduction as to why successful companies deploy HLS for vision and deep learning applications.
This webinar is part 1 of the webinar series “HLS for Vision and Deep Learning Hardware Accelerators”
What You Will Learn
- How HLS is used to implement a computer vision algorithm in either an FPGA or ASIC technology and the trade-offs for power and performance.
- How HLS is employed to analyze unique architectures for a very energy-efficient inference solution such as a CNN (Convolutional Neural Network) from a pre-trained network.
- How to integrate the design created in HLS into a larger system, including peripherals, processor, and software.
- How to verify the design in the context of the larger system and how to deploy it into an FPGA prototype board.
Who Should Attend
- RTL Designers or Project Managers interested in moving up to HLS to improve design and verification productivity.
- Architects or hardware-aware algorithm developers in the field of image processing, computer vision, machine and deep learning, that are interested in rapid and accurate exploration of power/performance metrics.
- New project teams with only a few hardware designers and multiple software experts that want to rapidly create high-performance FPGA or ASIC IP for computer vision or deep learning markets.