According to an IDC whitepaper sponsored by Seagate, the global datasphere will grow from 33 zettabytes (one zetabye = one trillion gigabytes) in 2018 to 175 zettabytes by 2025. This whitepaper also reports that today, more than 5 billion consumers interact with data every day. By 2025, that number will be 6 billion, or 75 percent of the world’s population.

Clearly, there is a data explosion occurring with an ever-increasing need for dramatic bandwidth improvement to keep up. Delivering this capability has two challenges — working silicon that can deliver the required performance and a test fixture that allows system designers to verify performance in their target application. In this webinar, we’ll discuss both challenges. Technology, methodology and strong collaboration all play a part.

Our discussion will focus on PAM4 (pulse amplitude modulation) systems operating at 56 Gigabits per second and beyond. PAM4 is a modulation technique whereby four distinct pulse amplitudes are used to convey the information.


  • The challenges of high-performance communications, introduction by Dan Nenni, SemiWiki
  • Designing a test board to deliver performance — the Apollo mission model, Al Neves, Wild River Technology
  • Delivering the required connectivity, Matt Burns, Samtec
  • Putting it all together with our SerDes, Tim Horel, eSilicon

Note: All webinar attendees will receive a new white paper:
Meeting the demands of PAM-4 systems at 56Gbps and beyond
Technology, a winning methodology and the desire to collaborate all matter

The webinar will be presented at 8:00-9:00 AM and 6:00-7:00 PM Pacific Daylight Time on Thursday, July 11, 2019.

Please register for only one webinar. If you register twice, the system will replace your first registration with your second. If you would like to register for both, please contact Sally Slemons at

Meet our speakers


Dan Nenni-20190617-113x170 Dan Nenni, CEO and Founder,
Dan has worked in Silicon Valley for the past 34 years with computer manufacturers, electronic design automation software, and semiconductor intellectual property companies. He is the founder of (an open forum for semiconductor professionals) and the co-author and publisher of “Fabless: The Transformation of the Semiconductor Industry,” “Mobile Unleashed: The Origin and Evolution of ARM Processors in our Devices” and “Prototypical: The Emergence of Prototyping for SoC Design.” Daniel is an internationally recognized business development professional for companies involved with the fabless semiconductor ecosystem.

Wild River Technology

Al-Neves-113x170 Al Neves, Founder and Chief Technologist, Wild River Technology
Al has 30 years of experience in the design and application development of semiconductor products focused on jitter and signal integrity analysis. He has been successfully involved with numerous business development and startup activities for the last 13 years. Al is involved with the signal integrity community as a consultant, high-speed system-level design manager and engineer. Recent technical accomplishments include development of platforms and methods to improve 3D electromagnetic correspondence to measure-based methods, including advancing time and frequency domain calibration methods. Al focuses on measure-based model development, package characterization, high-speed board design, low jitter design, analysis and training. He earned a BS in Applied Mathematics at the University of Massachusetts.


burns_matt_large-113x170 Matt Burns, Product Marketing Manager – High Speed, Samtec
Matt develops go-to-market strategies for Samtec’s high-speed interconnect solutions. Over the course of the last 20 years he has been a leader in design, application engineering, technical sales and marketing in the telecommunications, medical and electronic components industries. He holds a BS in Electrical Engineering from Penn State University.


Tim-20190618-113x170 Tim Horel, Director of Field Applications, eSilicon
Tim focuses on SerDes IP applications at eSilicon. Prior to eSilicon, he was a senior manager and principal engineer at Oracle, focusing on SerDes technology. Tim has also held hardware design and operations leadership positions at abound logic, Tabula, Sun Microsystems and AMCC. Tim began his career at IBM. He holds a BE EE degree with a minor in Computer Science from the State University of New York at Buffalo.

Register 8 AM    Register 6 PM