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Webinar: From HLS Component to a Working Design
October 15, 2019 @ 10:00 am - 11:00 am
Complex algorithms do not exist in a vacuum. After HLS is used to create an RTL component, to be useful, it needs to be integrated into a larger system. This means connecting it to other components, a processor, and even software. Once integrated, the system needs to be verified. The verification of the complete environment does not just mean functional correctness, but also needs to consider performance, and in some cases power. This webinar details approaches to integrating accelerator blocks into processor-based sub-systems, interfacing to software, and verifying the accelerator in the context of the larger system. It also covers deploying the system onto a FPGA prototyping board.
This webinar is part 4 of the webinar series “HLS for Vision and Deep Learning Hardware Accelerators”
What You Will Learn
- How HLS is used to implement a computer vision algorithm in either an FPGA or ASIC technology and the trade-offs for power and performance.
- How HLS is employed to analyze unique architectures for a very energy-efficient inference solution such as a CNN (Convolutional Neural Network) from a pre-trained network.
- How to integrate the design created in HLS into a larger system, including peripherals, processor, and software.
- How to verify the design in the context of the larger system and how to deploy it into an FPGA prototype board.
Who Should Attend
- RTL Designers or Project Managers interested in moving up to HLS to improve design and verification productivity.
- Architects or hardware-aware algorithm developers in the field of image processing, computer vision, machine and deep learning, that are interested in rapid and accurate exploration of power/performance metrics.
- New project teams with only a few hardware designers and multiple software experts that want to rapidly create high-performance FPGA or ASIC IP for computer vision or deep learning markets.