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Webinar: Designing Methodologies for Next-Generation Heterogeneously Integrated 2.5- and 3D-IC Designs

June 23 @ 2:00 PM - 3:00 PM

Overview

After years of steady SoC and ASIC aggregation packing functionality into a large single die, the semiconductor industry can no longer meet growing performance demands. In the face of power, performance, and area constraints and reticle limits, and with the cost of production at advanced nodes skyrocketing, there is renewed interest in a disaggregated approach to chip development.

In this Mandarin webinar, we will discuss the design methodologies needed for next-generation advanced multi-chip(let) packaging, including determining:

· Layout tool/flow best for your design type
· Top-level design aggregation and management
· Test and verification of advanced multi-chip(let) IC packages
· Cross-domain electrical/thermal modeling

*This webinar will be conducted in Mandarin.

The whole process design welcomes the new realm of heterogeneous integration of 2.5D and 3DIC design

In the past many years, the semiconductor industry has packaged stable SoC and ASIC aggregate functions into chips, but as Moore’s Law is gradually approaching the physical limit, it is unable to meet the ever-increasing performance requirements. Faced with low power consumption, high efficiency, small size and mask restrictions, and the soaring production costs of advanced processes, the industry has begun to renew interest in wafer development methods. “Heterogeneous Integration” has become the hottest topic, and it is expected to be a semiconductor. An important driving force for the next wave of market growth.

As advanced packaging becomes more and more complex, it is difficult for packaging or chip design to be completed with existing design tools. The design methodology must be changed to achieve a better system-level integrated design process. Cadence has established a complete and automated design methodology for IC, package to circuit board, whether it is for 2.5D/3D or chiplet-based system design, Cadence has established a solution that can meet the design needs of heterogeneous integration, and is committed to Promote the “smart system design and realization” strategy to help the industry meet a new level of heterogeneous integration.

Cadence will hold an online seminar on “Full Process Design Welcomes the New Realm of Heterogeneous Integration of 2.5D and 3DIC Design”. Online exchanges are welcome!

*Online seminars will be delivered in Chinese

Date and Time

Tuesday, June  23, 2020
Time: 14:00-14:50  (Taipei Time)

Agenda-
June 23, 2020 (Tuesday) (Taipei time)

14:00-14:40

The whole process design welcomes the new realm of heterogeneous integration of 2.5D and 3DIC design

Designing Methodologies for Next-Generation Heterogeneously Integrated 2.5- and 3D-IC Designs

14:40 – 14:50

Q&A

Speaker: 

Julian Sun, Product Marketing Director, Cadence

Sun Zijun, Director of Product Technology, Cadence