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SemiWiki WEBINAR: An Introduction to the Capabilities of StarVision Pro for Mixed-Signal Designs

September 12 @ 10:00 am - 10:45 am

Overview:
This webinar provides an introduction to the capabilities of Concept Engineering’s StarVision Pro and how it can be used to assist engineers on visualizing and debugging various forms of netlists and assist in speeding up simulation time. More details can be found on the registration page here.

What you will learn:

VISUALIZE: Render schematics on the fly for VHDL/Verilog/Spice level netlists to understand the function of design easily. Supported formats include Verilog, VHDL, SystemVerilog, Liberty, SPICE, HSPICE, Spectre, Calibre, CDL, DSPF, & SPEF.
PRUNE: Extract, navigate and save critical timing paths/fragments of design as Verilog/Spice/SPEF netlists with the ‘cone view,’ for reuse as IP or external use in partial simulation.
CLOCK DOMAIN ANALYZER: Visualize and detect different clock domains in the design.
CROSS-PROBE: Drag & drop selected components/nets between all design views (schematic, logic cone, Parasitic window, and source code view and simulation data) to cross probe and shorten debug time, especially during tape-out for full-chip debug. Also the ability to cross-probe analog and digital simulation data on the netlist.
PARASITIC: Visualize and analyze parasitic networks (Post layout formats: DSPF, RSPF, SPEF) and create SPICE netlists for critical path simulation.
NETLIST REDUCTION: Instantly turn off/on parasitic structures in SPICE circuits for better comprehension of CMOS function.
SKILL EXPORT: Export schematics and schematic fragments into Cadence Virtuoso.
SOC OR MIXED SIGNAL DESIGN: Visualize, Debug and Analyze the RTL, GATE, and SPICE Design in one cockpit!
DOCUMENT: Generate design statistics & reports: Instance & primitive counts
TCL API: Extend the functionality of StarVision to match project needs by interfacing with the open database through TCL scripts and in batch mode
IDENTIFY DIFFERENCES IN SCHEMATICS: Extend the capabilities of the tool to identify differences between designs.

Who should attend:

  • Analog Design and Verification Engineers / Managers
  • Mixed-Signal Design Engineers and Managers
  • RTL Design & Verification Engineers / Managers
  • Layout Verification Parasitic Extraction Engineers
  • IP Procurement Teams

Details

Date:
September 12
Time:
10:00 am - 10:45 am
Website:
https://attendee.gotowebinar.com/register/5428220037442561804?source=SW-CN-1-SW-cal