Visualizer Coverage: Debug and Visualize All Your Coverage Without Leaving Your House – Even If You Can

Overview

Trying to figure out how to achieve 100% coverage closure?

Wondering how to view coverage, find issues and fix them all at one place?

Visualizer Debug Environment gives the user many ways to analyze and improve coverage with ease. It provides an unbeatable coverage solution by gathering powerful core functionality with smart UI. We have taken advantage of the existing richer visualization capabilities that Visualizer has, to enhance data representation during coverage analysis. It is built with improved capacity and performance to handle exhaustive designs with large coverage data. The visualization tools in Visualizer display UCDB results for both code coverage and functional coverage. Using Visualizer now users can analyze coverage and debug coverage issues with the help of design and waveform data available in Visualizer, all at once.

This session will focus on coverage features such as:

• Coverage Viewing and Reporting
• Coverage debugging mode
• Two-Step Exclusion Management
• Testplan Tracking and Test Analysis

What You Will Learn

• Using Testplan Tracker in Visualizer to analyze the testplan
• Finding uncovered items using code and functional coverage windows and fixing them using coverage debugging mode
• Applying exclusions and saving them for future use using  the Two-step exclusion flow
• Technical demonstration

ABOUT THE PRESENTER

Athira PanickerAthira Panicker is a Product Engineer for Coverage and Verification IQ at Mentor Graphics. She has experience in functional verification, verification tools, and methodologies. Ms. Athira holds a Masters in Electrical and Computer Engineering from Portland State University.

Who Should Attend

• IP, FPGA and SOC Design & Verification Engineers
• Engineering Managers
• Program Managers

Products Covered

• Visualizer™ Debug Environment