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Versal ACAP Workshop Online
May 24, 2022 - May 25, 2022
This webinar meets 2 times.
May | |
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Tue, | May 24, 2022 8:30 AM – 12:30 PM PDT |
Wed, | May 25, 2022 8:30 AM – 12:30 PM PDT |
Workshop Agenda: Delivered across 2 half-day sessions
– Versal ACAP: Structural Overview Big picture overview, processing engines, connections and capabilities.
– Intro to AI Engines Scalar and vector processing unit, SIMD data-path, multi-kernel control and communication
– PS Overview Introduce the A72 and R5F processors, MPSoC migration, the role of the PMU, device boot, etc.
– PL Fabric The traditional FPGA fabric, encompassing enhanced layout, clocking, and slice capabilities
– NoC Resources Overview for Versal ACAP communication backplane, data-transfer, DDR controller
– Enhanced DSP58 New features, layout and operational modes for PL fabric-based DSP building blocks
– AIE Vector Datatypes Declaring vector datatypes required for the high-performance SIMD data-paths
– Intrinsic(s) Coding Introduction to proprietary syntax for maximizing AI engine vector processing
– FIR Filter Coding for AIE A step-by-step working example for 1GHz+ FIR filter targeting AI engine
Please come prepared to actively participate and engage directly with the workshop facilitator. Thanks to Xilinx for sponsoring this training – it is now available to attend Free of Charge.
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