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The Easy Path to Maximum Performance-per-Watt on Arm® Neoverse™ Cores With Fusion Compiler
May 26, 2021
Arm’s family of Neoverse™ cores – the latest of which, the Neoverse N2 and V1 – target high-end infrastructure applications and are set to play a central role in the next generation of data center, high-performance computing (HPC), 5G and AI SoCs. Extracting the maximum performance-per-watt for SoCs targeting these applications demands the best tools, flows, and methodologies. In this seminar, you will gain deep insight from Arm® and Synopsys experts into the Neoverse N2 and V1 architecture and how Synopsys has deployed unique enabling technologies in Fusion Compiler™ to efficiently deliver on the promise of these latest advanced cores from Arm.
Lisa Minwell is the Director of Product Marketing at Arm Inc., Lisa is responsible for physical IP solutions for the Infrastructure segment. Previously, Lisa held various managerial positions with eSilicon, Synopsys, Virage Logic and Motorola. Lisa holds a Bachelor of Science in Microelectronic Engineering from Rochester Institute of Technology, Rochester, New York.
Dale Lomelino is a Sr. Staff Applications Engineer for the Arm Solutions Group (ASG) at Synopsys. In this role, Dale collaborates closely with Arm to develop RTL-to-GDSII flows for Arm CPUs and the supporting, DynamIQ™ Shared Units (DSUs). Dale has worked at Synopsys for over 16 years; previously, he worked at Philips/VLSI Technology. Dale holds an MSEE degree from the University of Illinois.