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Tessent SiliconInsight ATE-Connect: Bending the bring up schedule curve in your favor

July 28, 2020 @ 8:00 AM - July 30, 2020 @ 9:00 AM

Register For This Web Seminar

Online – Jun 16, 2020
5:00 PM – 6:00 PM US/Pacific
Online – Jul 28, 2020
8:00 AM – 9:00 AM US/Pacific


With  the number of IP blocks and complexity of designs increasing, how do you improve your TTM for debug of a test program to production?  Teradyne and Mentor continue to innovate with Tessent IJTAG by releasing platform support for UltraFLEX+ and enhanced capability with Tessent for embedded memory MEMBIST.  Teradyne’s PortBridge technology enables the UltraFLEX family of production testers to achieve optimized TTM by enabling streamlined program debug, production operation, and lab correlation to test for critical IP blocks.  Learn about how Teradyne’s UF+ innovations will enable future EDA innovations which will accelerate TTM on your next silicon.

Joining us in this webinar will be Marc Hutner, Teradyne and Matt Knowles of Mentor, A Siemens Business.

What You Will Learn

  • Current and future challenges for complex SoC bring up
  • How EDA software and ATE hardware tools are working together
  • IJTAG and MBIST case studies showing bring up from weeks to immediate results
Matthew Knowles, Ph.D.Product Marketing Manager, Tessent Operations

Matthew Knowles is the product marketing manager for the Tessent Operations products at Mentor, a Siemens Business. He has worked in various product management and marketing roles throughout the semiconductor industry for the last 23 years. From 1997 to 2006, Matthew held various leadership roles at Intel.  Previous to joining Mentor from 2006-2016, he was instrumental bringing several new products to market for physical failure analysis (FEI, now ThermoFisher) laser micro machining (ESI) and wafer metrology (Zygo, now Nanometrics).    His current focus is on diagnosis, yield analysis, and silicon bring up, debug and analog fault simulation. He earned his Ph.D. in Physical Chemistry from the University of Colorado, Boulder, Colorado.

Marc HutnerDfX Systems Engineering, Semiconductor Test Division, Teradyne

Marc Hutner is the DfX Systems Engineering responsible for design to test solutions that accelerate ATE debug.  He has worked at Teradyne for 20 years in a variety of engineering and technical management positions. This includes analog IP design, ASIC development management, Instrument design, ATE system definition and technical product management.  He also is a contributor to the Heterogeneous Integration Roadmap for semiconductors for test (formerly the ITRS roadmap) and has contributed

Who Should Attend

  • Test engineers
  • DFT bring up engineers and managers
  • Product engineers
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