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Taking SystemVerilog Arrays to the Next Dimension
June 5, 2020 @ 8:00 AM - 9:00 AM
Register For This Web Seminar
8:15 AM – 8:45 AM US/Pacific
Chris Spear, Principle Instructor, presents a detailed description of the various array types in the SystemVerilog language, and how to pick the right ones for your testbench. SystemVerilog has many dynamic data types, and you will learn which ones to choose for scoreboards, sparse memories, hash arrays, and more. As a result, your testbench code will be easier to understand and reuse, run faster, and consume less memory. These array types are part of the building blocks for verification methodologies including UVM.
What You Will Learn
- How to apply the string type, including formatting and parsing
- The differences between vectors and arrays
- When to choose a fixed size array and a dynamic array
- Modeling scoreboards with queues
- Modeling large memories with associative arrays
- A simple guide to choosing between these array types
- Built-in SystemVerilog methods to search sort, and reduce arrays
Chris SpearChris brings over twenty five years of EDA expertise to Mentor customers. Holding a degree in electrical engineering from Cornell University, Chris has developed deep roots in the EDA industry, including as a Principal Application Consultant with Synopsys. Chris is also an industry author, writing the 2012 best-selling “SystemVerilog for Verification” and developing the IEEE standard for random seeding and File I/O PLI package that is part of SystemVerilog. Having taught thousands of engineers around the world, Chris is driven by a passion for learning new techniques and then helping others learn best practices for hardware verification. Outside of work, you may see Chris bicycling over 12,000-foot mountain passes.
Who Should Attend
- Verification Engineers who are new to SystemVerilog, and also those looking to tune up their coding talents
- Design Engineers who want to expand their verification skills