System Planning and Implementation for Different 3D-IC Design Styles

Overview

System planning is a major part of the multi-chiplet design. Whether it’s a 2.5-D configuration with an interposer or full-stacked 3D design mounted on a package, it is important to have an automated way to do bump assignment and optimization along with 3D structures implementation. With methodology evolving for different types of designs, a top-down and a bottom-up approach for implementation is possible. In this session, learn about the different approaches to 3D partitioning, implementation, and unique capabilities available with Integrity 3D-IC platform for bump planning, interposer routing, and top-down 3D partitioning and implementation available with Cadence’s Integrity 3D-IC platform.

Sessions

Date and Time:
Wednesday, March 9

EMEA
9:00 GMT / 10:00 CET / 11:00 EET and Israel / 14:30 IST

North America
10:00am PT / 1:00pm ET

Register Here