Static Timing Signoff and Model Generation for Complex Analog/Mixed-Signal Designs

Designing complex, mixed-signal IPs is extremely challenging. Traditionally, timing is verified using measurements extracted from dynamic simulations. However, as this is vector-dependent, it relies heavily on designer expertise to select the correct set of critical paths. Often, this approach does not cover all the necessary timing checks across all operational modes and process corners. Failing to check the fastest and slowest paths in the design can lead to silicon failures. This webinar discusses a timing signoff methodology that uses transistor-level static timing analysis to augment dynamic simulation. This methodology performs validation for all timing checks (I/O timing, internal timing) including signal integrity effects (crosstalk delay and noise) and parametric on-chip variation (POCV). It discusses how static timing can be used to quickly create block-level timing models (.lib) so that that AMS IP blocks can be used by a digital implementation flow.

PRESENTERS:
Jim McCanny joined Synopsys in November 2018 and is an R&D Director leading the development, product engineering, marketing and application support for transistor-level signoff. Jim has been in the EDA industry for 30+ years in various roles in R&D and product marketing, mostly involving timing/noise analysis and cell/macro library characterization. He is the former CEO of Altos Design Automation.

Andy Le is a Sr. Staff Engineer at Synopsys working on the development of advanced methodologies, flows, and technology integration along with technical support, deployment and proliferation of NanoTime for key customers worldwide.  Andy has been in the semiconductor and EDA industries for 30+ years in variety of positions, including director of Product Engineering, director of SoC Engineering, CAD manager, and Sr. Staff Design Engineer working on EDA tools development, and advanced chip design flows.