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Seminar: Domain-Specific Processor Design using ASIP Designer

December 9, 2019 @ 12:30 PM - 5:30 PM

Join us December 9, 2019
12:30 – 5:30 pm (lunch included)

Synopsys
800 N. Mary Ave. Bldg. 1
Sunnyvale, CA 94085

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The RISC-V initiative has raised increased awareness about the design of domain-specific or application-specific processors, which implement a specialized instruction set architecture (ISA), often starting from a baseline ISA such as RISC-V.

But designers are faced with the challenges of determining the best ISA for their specific application, how to get to a compiler and a simulator for the specialized architecture, and how to know if the target performance can be reached.

Synopsys ASIP Designer is a design tool that automates the design of application-specific processors. Starting from a single processor specification that allows to model standard ISAs such as RISC-V as well as any kind of specializations, designers get a cycle-accurate simulator, debugger and an optimizing C/C++ Compiler, all supporting the specialized ISA. This allows for a compiler-in-the-loop based tuning of the processor specification, using the real application code to benchmark the performance. From the same specification, the RTL code is generated, which allows to measure the gate count and to identify critical paths in the design.

Top semiconductor and systems companies worldwide deploy ASIP Designer for innovative designs on aggressive schedules with limited design teams.

Join us for this free half day seminar, beginning with a networking lunch and followed by technical presentations from Synopsys technical experts on topics including 5G, AI, and security.

Details

Date:
December 9, 2019
Time:
12:30 PM - 5:30 PM
Website:
https://www.synopsys.com/designware-ip/processor-solutions/asips-tools/asip_seminar.html

Organizer

Synopsys
Website:
https://www.synopsys.com/

Venue

Synopsys
800 N. Mary Ave. Bldg. 1
Sunnyvale, CA United States
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