RISC-V Summit 2020

CONTRIBUTE. COLLABORATE. COMMERCIALIZE.

Save the dates now for RISC-V Summit 2020: December 8-10, Members Only Day: December 7

Attend RISC-V Summit in San Jose to be part of the disruptive force transforming the microprocessor IP market through open standard collaboration. Registration will be opening soon – stay tuned!

2020 SESSION TRACKS
This year’s program will feature exciting new projects and implementations, technical capabilities and commercial implications around the following key topic areas

Community, Ecosystem and Task Groups
Track Chair: Drew Fustini, BeagleBoard.org Foundation

Hardware Cores/SoCs
Track Co-Chair: Allen Baum, Esperanto Tech

Track Co-Chair: Chuanhua Chang, Andes Technology

Security & Functional Safety
Track Co-Chair: Jerome Quevremont,Thales Research & Technology

Track Co-Chair: Helena Handschuh, Rambus

Software & Tools
Track Chair: Arun Thomas, Draper Laboratories

System Architectures
Track Co-Chair: Andy Glew, SiFive

Track Co-Chair: Kevin Chen, Andes Technology

Verification
Track Chair: Simon Davidmann, Imperas Software

LEARN MORE ABOUT BECOMING A SPEAKER

ABOUT RISC-V SUMMIT
The third annual RISC-V Summit will highlight the continued rapid expansion of the RISC-V ecosystem, with both commercial offerings and exciting open-source developments. Newcomers to the RISC-V world, as well as the seasoned developers who are interested in broadening their toolsets are invited to choose from the broad range of tutorials. The conference program will feature keynotes from the leaders in the field as well as stimulating panel discussions from a range of both well-established and up-and-coming companies, as well as researchers from several of the leading academic institutions.