Questa Clock/Reset Domain Crossing Verification / Mentor Functional Safety Compliance – What’s New in Functional Verification from Mentor: Session 5

Confronting Inevitability:  Finding Clock and Reset Issues Before They Find You:

The aggressive clock, reset and power design techniques and methodologies that were once only the domain of bleeding-edge products are common-place today, as driven by market requirements. Errors in clock, reset and power designs are costing projects needless additional thousands if not millions of dollars before getting into production. This session will show how Questa’s clock- and reset-domain crossing solution will help you avoid costly design flaws and accelerate your time to market.

What You Will Learn 

• Identify the potential cost or opportunity cost of missed clock or reset domain crossings issues
• Understand the full scope of clock and reset synchronization issues and how to find them
• Recognize the difference between a full solution and a partial one

Mentor + Siemens Provides Solutions and Expertise to Achieve Rapid Safety Compliance:

When verifying safety critical systems, the stakes are raised in ensuring that bugs/defects are not introduced into production with many standards striving for zero defective parts per million. The powerful combination of Mentor’s functional verification and functional safety products together with Siemens’ lifecycle management tools provide built-in guidance and automation helping you navigate the difficult waters of safety compliance.

What You Will Learn 

• The three pillars of FuSa and activities required to demonstrate the achievement of functional safety
• A functional safety methodology to efficiently and systematically execute your safety lifecycle
• How Mentor and Siemens solutions automate and guide a project team through the challenges of a safety lifecycle

ABOUT THE PRESENTERS

Chris GilesChris is a member of the DVT Product Marketing team, managing the Design Solutions product line, including the CDC+RDC product lines as well as the HDL Designer Series. Chris comes to Mentor from the user community, with decades of experience in IP and ASIC/SoC/FPGA R&D and management, with products deployed in consumer, military, compute and storage markets and at companies such as Hewlett Packard Enterprise, Honeywell, Seagate, Micron, NEC and LSI Logic. The author of 18 patents in areas such as hardware virtualization, security, processor architecture, synchronization schemes, and hardware prototyping, Chris received an MSEE from Stanford University in California and a BSEE from Rice University in Texas.

Jacob WiltgenJacob Wiltgen is the Functional Safety Solutions Manager for Mentor, A Siemens Business and responsible for defining and aligning functional safety technologies across the portfolio of IC Verification Solutions. He holds a Bachelor of Science degree in Electrical and Computer Engineering from the University of Colorado Boulder. Prior to Mentor, Jacob has held various design, verification, and leadership roles performing IC and SOC development at Xilinx, Micron, and Broadcom.

Products Covered

• Questa® CDC Verification
• Questa® Reset Domain Crossing (RDC) Verification

Who Should Attend

Design and Verification Engineers and Managers