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Protocol Verification with Questa VIP / Coverage Closure with Questa inFact
May 28, 2020 @ 4:00 PM - 5:00 PM
This is the third of a 5-part series on “What’s New in Functional Verification from Mentor.” Each session will be presented twice at the times shown above consisting of two half-hour presentations, with Q&A. Please register for the time that is more convenient for you.
Maximize Your UVM Productivity with Protocol-Aware Questa Verification IP
The Questa VIP library gives you everything you need to verify standard protocols in your UVM environment. With the new Configurator GUI, it’s now even easier to take advantage of these powerful verification components to maximize the effectiveness of your UVM verification.
What You Will Learn:
- How QVIP is architected for ease of use
- How the Configurator GUI simplifies QVIP setup and integration
- How QVIP automatically provides protocol-specific transaction debug
Find Bugs Earlier with Strategy-Guided Stimulus
Finding mismatches between design specification and implementation – bugs is a key responsibility of verification engineers. We care about two key aspects of design quality: ensuring that known use cases work properly, and checking that valid but unanticipated use cases don’t result in failures. In a typical constrained-random verification process, we are trying to accomplish both of these goals across the random-regressions and coverage-closure phases of the verification cycle. In this session, we will discuss the benefits of focusing on each of these activities independently, and see how strategy-guided stimulus helps to accomplish this.
What You Will Learn:
- How Questa inFact catches bugs early by focusing on achieving functional coverage goals
- How inFact’s goal-driven approach to stimulus generation can be used to take a structured approach to bug hunting
- How inFact increases regression efficiency
Munish GoyalMunish Goyal has spent almost 15 years in Pre-Silicon verification and post silicon validation, working at top semiconductor companies like Qualcomm, Freescale & ST Microelectronics. He holds a bachelor’s degree in Electronics & Communication from a premier institute in India. He spent good amount of his time doing SoC verification for ARM-based designs, developing expertise in CPU and peripheral verification before he moved into EDA, focusing on VIPs. For the past 10 years, Munish has been involved in the development and deployment of advanced Verification IPs. At Mentor, Munish leads the Questa Verification IP (QVIP) Product Engineering teams worldwide.
Matthew BallanceMatthew Ballance is a Product Engineer and Portable Stimulus Technologist at Mentor, A Siemens Business, working with the Questa inFact Portable Stimulus product. Over the past 19 years in the EDA industry, he has worked in product development, marketing, and management roles in the areas of HW/SW co-verification, transaction-level modeling, IP encapsulation and reuse, and Portable Test and Stimulus.
Who Should Attend
Design and Verification Engineers and Managers