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Prevent and Eliminate IR drop and Power Integrity Issues using Redhawk Analysis Fusion

March 31, 2020 @ 10:00 AM - 11:00 AM

Tue, Mar 31, 2020 11:00 AM – 12:00 PM MDT

*** This webinar requires that you register with your work email address ***

As we move towards advanced nodes where supply voltage reduces and transistors shrink in size, reliability challenges increase significantly. Designers see more IR drop and power integrity issues, and we can no longer wait until final signoff stages of the flow to uncover these violations as it gets too late to fix them. Traditional design flows have led to silicon failures/re-spins and missed targets for power-performance-area (PPA). It has therefore become essential to tackle these violations earlier in the design cycle so that we have a design which is correct by construction.

In this webinar, we will illustrate how comprehensive block-level signoff accuracy, robust optimization techniques, and greater throughput from the RedHawk-SC integration, empower physical design teams with significant productivity and PPA gains. We will share customer deployment experiences and their testimonials on multiple tape-outs at advanced process nodes.


Rahul Deokar is the Director of Marketing and Business Development for the Synopsys Fusion Design Platform with focus on Signoff Products, including RedHawk Analysis Fusion. Previously, he held numerous marketing roles at Cadence, led static timing analysis development at Ambit Design, and drove transistor-level optimization at Lucent Technologies Bell Labs.

Marc Swinnen is an EDA professional with experience in a wide array of digital and analog design technologies. He obtained a masters in electrical engineering from IMEC and the Catholic University of Leuven in Belgium, and an MBA from San Jose State University. Before joining Ansys Marc worked in Marketing and Support Management positions at Cadence, Synopsys, Azuro, and Sequence Design.

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March 31, 2020
10:00 AM - 11:00 AM
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