SoC designers, looking to get a jump start on their PCI Express (PCIe) 6.0 designs must be aware of several new considerations in addition to doubling of the data rate to 64 GT/s. Accessing a complete IP solution that offers optimized performance and seamless interoperability between the controller and PHY, achieving timing closure at 1+ GHz, and understanding the impact of the new PCIe 6.0 features including FLITs, new low power state, and PAM-4 signaling are just a few of the topics that we will discuss in this Synopsys webinar.

Attendees will learn about:

  • Key features of PCIe 6.0 including FLITs, power state and PAM-4 signaling
  • Design considerations and IP implementation for a successful migration to PCIe 6.0
Gary Ruggles
Sr. Product Marketing Manager

Gary Ruggles is the Sr. Product Marketing Manager for PCIe, CCIX, and SATA Controllers. Gary has over 25 years of experience in the semiconductor industry, and has spent the last 19 years in sales, marketing, and business development roles for multiple semiconductor IP companies. Gary has an extensive background in electronics and integrated circuit design and began his career as Assistant Professor of Electrical and Computer Engineering at North Carolina State University, where he taught courses in Solid State Physics and VLSI Processing. Gary holds a PhD in Electrical Engineering from Penn State University.