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PCB Systems forum 2019 India

August 6, 2019 @ 8:00 AM - August 9, 2019 @ 5:00 PM

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Establishing an effective PCB systems design validation process reduces design spins and increases product quality.

Increasing performance requirements coupled with a pressure to improve product quality are driving engineering teams to consider alternatives to their current validation approach. Best-practice design processes validate the digital twin (a model of your design) early and often to minimize re-spins and actually shorten the overall design cycle. This ‘shift-left’ approach enables design engineers and layout designers to validate within their native environment, minimizing the bottleneck waiting for specialist reviews, and freeing the specialists to resolve the remaining critical issues. This process allows engineering teams to better cope with increasing complexity and focus their efforts on product innovation.

This event will cover research on best-practice process strategies (as well as implications of avoiding them). Case studies will show how engineering teams have deployed an ‘optimal’ automated validation process to accelerate sign-off. Analysis technologies that could be deployed within any ECAD flow will be discussed, including multi-board schematic, signal and power integrity, analog/mixed signal, thermal, vibration and manufacturability.

Solutions Covered

  • Automated multi-board schematic analysis – Full inspection of all schematic nets to increase design quality and reduce re-spins
  • Rule based error identification enabling checks for potential issues early and often during the layout implementation. Quickly layout and routing issues that could lead to SI, PI, EMI and other problems
  • Design to manufacturing optimization with comprehensive DFM analysis, incorporated into your PCB design process
  • Signal integrity analysis (pre and post layout)
  • Power integrity (DC and AC) analysis for correct implementation of the power distribution network
  • 3D, broadband, full-wave electromagnetic field solver for SI, and EMI
  • Integrated testability analysis – Reduce overall cost of test by addressing testability considerations in schematic capture and layout
  • Analog / mixed-signal simulation (inclusive of PCB material effects through automated parasitic extraction)
  • Design exploration to automatically vary actual parameters in a design concept and identify high performing design option

Who Should Attend

  • PCB Designers and Managers
  • CAD Managers and CAD IT Managers
  • High-speed Specialists
  • EMI/EMC Signoff Engineers
  • Electrical engineers and Managers
  • Design Engineers


09:00 AM-09:30 AM  Industry Keynote
09:30 AM-10:00 AM   Welcome and Update of the Siemens/Mentor Vision in Digital Twin area
10:00 AM-10:45 AM   Eliminate Schematic and Layout Design Errors with Automated Verification
10:45 AM-11:00 AM   Tea Break
11:00 AM-12:00 AM   Managing Your WIP (Work-in-Progress) in PCB Design Life cycle
12:00 PM-01:00 PM   Solving DDR and SerDes Challenges with Advanced Simulation and Protocol based Verification
01:00 PM-02:00 PM   Lunch
02:00 PM-03:00 PM  Collaborative Circuit Design, Placement and Routing of complex PCB’s
03:00 PM-03:15 PM   Tea Break
03:15 PM-04:00 PM   Introduction to Next Generation DFM and Optimi



124/1 J.N.Salai  I  Guindy
Chennai 600032 | India


Adjacent to Aga Khan Palace,
88 Nagar Road, Kalyani Nagar,
Pune – 411006, India
T: +91 20 6606 8867
F: +91 20 4141 1235


23, HAL Old Airport Rd
HAL 2nd Stage,
Kodihalli, Bengaluru
Karnataka 560008

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August 6, 2019 @ 8:00 AM
August 9, 2019 @ 5:00 PM


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