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Overcoming System-Level 3D-IC Electrical and Thermal Challenges

April 6

Overview

Electronics products with 3D-ICs face growing system challenges related to signal, power, and thermal integrity. Design density can lead to performance issues caused by heat, crosstalk, and power noise.

Addressing these concerns through simulation during system planning and continuing through signoff will accelerate the 3D-IC design cycle by avoiding expensive design re-spins. Therefore, it is important to have a vision of thermal gradients, signal quality, and power delivery across the chiplets, packages, and PCBs to not only address any risks, but also optimize the design’s TSV locations for maximum performance. This talk will cover:

· System analysis challenges of 3D-IC design

· 3D-IC chip-centric thermal analysis using Voltus™ solution and Cadence Celsius™ Thermal Solver

· 3D-IC package PCB thermal analysis

· 3D-IC interconnect modeling

· System-level signal quality and power distribution network (PDN) signoff

Sessions

Date and Time:
Wednesday, April 6

EMEA                                

9:00 BST / 10:00 CEST / 11:00 EEST and Israel / 13:30 IST

North America                                                                                                                                                                                                                                                                                                10:00am PT / 1:00pm ET

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