Optimizing power and increasing data throughput in advanced multi-core AI/ML/DL devices

If you are working on complex Artificial Intelligence (AI) or Machine Learning (ML) or Deep Learning (DL) designs using advanced node processes, you will understand the motivations for optimising CPU utilisation, device power and processing speed. Cutting-edge AI, ML & DL chips, by their very nature, are susceptible to intra-die process variability. Designers are often walking a fine line between optimal performance and failure.

This webinar from Moortec looks at how close real-time analysis of dynamic conditions, as well as identifying process corners, using embedded in-chip monitoring fabrics based on advanced node processes can greatly improve the power consumption, data throughput and computational performance of the overall system design.

Topics covered will include how tight dynamic guard-banding will enable improvement for the optimisation of multi-core utilisation, thermal load balancing and fine-grain SVS/AVS control, whilst the device is in mission-mode.

Due to their experience and dedication to In-Chip Monitoring, Moortec are able to support companies who are operating at the cutting edge of AI and Machine Learning chip design. Such companies have utilised Moortec’s highly accurate, highly featured sensors within their in-chip monitoring subsystem to ensure optimal performance and enhanced reliability.

Moortec are global leaders for innovative in-chip monitoring technologies and sensing fabrics. The company is dedicated to maximizing performance, optimizing power utilization, and enabling highly accurate in-chip analytics across many sectors, including Data Center, AI, HPC, Automotive and Consumer applications.

SPEAKERS
Ramsay Allen, VP of Marketing at Moortec Semiconductor
Richard McPartland, Technical Marketing Manager at Moortec Semiconductor