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Optimize 22nm SoC Power & Performance with DesignWare Foundation IP & Fusion Compiler
For their next-generation SoCs, system architects are moving from 28nm to 22nm to improve power and performance. Derived as an optical shrink from the 28nm HPC+ platform, the 22ULP technology offers the power/performance trade-off typically sought after by consumer, and automotive applications, while the 22ULL technology provides significant power reduction crucial for designs in the IoT and wearables market segments. To develop the most competitive SoCs in these processes, designers should choose optimized Foundation IP (embedded memories, standard cell libraries and GPIO) for the highest possible performance with lowest power and area. The process technology benefits of leading 22nm processes, combined with the broad portfolio of highly optimized DesignWare Foundation IP and Fusion Compiler, can accelerate the process of moving to the next planar node.
Join this presentation to hear:
- How Unified RTL-to-GDSII optimization engines (Fusion Compiler) unlocks new opportunities for performance-per-watt power results
- How designers use the combination of Fusion Compiler and DesignWare Foundation IP to cut power and increase performance
- How differentiated embedded memories and logic libraries can deliver the required performance while minimizing power