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Optimal circuit sizing strategies for performance, low power, and high yield of analog and full-custom IP
February 2 @ 10:00 AM - 11:00 AM
*COMPANY EMAIL IS REQUIRED FOR REGISTRATION*
Semiconductor companies designing ICs for smart phones, automotive and industrial applications, CPUs, GPUs and memory components all employ teams of custom IC designers to create the highest performance chips at the lowest costs. Efficient design for yield is a key capability of a design team that meets time-to-market requirements and is cost-effective.
When designing analog/mixed-signal, RF and digital full custom IP, designers must consider many influence factors and effects, such as temperature and supply voltage variation, on-chip variation and process variation in the manufacturing process.
Besides creating a circuit topology, full custom design engineers must calculate device parameters such as MOS geometries and resistor values, also commonly called sizing the circuit. Sizing circuits to meet specs at all process corners and operating conditions while simultaneously minimizing power consumption and/or area has become a major challenge in full custom design, that many circuit designers struggle with on a daily basis.
In this webinar we will discuss the full custom sizing workflow, addressing:
- analog/mixed-signal vs full-custom digital circuit sizing
- balancing difficult spec trade-offs at every PVT corner
- algebraic equation solving vs numerical solvers
- machine learning and iterative optimization vs the random spice monkey
- optimizing for low power and small area with high parametric yield
- saving designers’ effort and reducing runtime by efficient automation
Speaker: Michael Pronath (MunEDA)
Speaker Bio: Michael is VP of Products & Solutions at MunEDA, and author and co-author of several international publications about methods of analog integrated circuit design and testing of mixed-signal circuits.
This webinar is in partnership with SemiWiki and MunEDAShare this post via: