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Navigating Between DDR5, LPDDR5, and HBM2/2E IP to Meet Your Design Goals

June 23 @ 10:00 AM - 11:00 AM

Don’t miss this opportunity to hear from Synopsys’ IP senior executives and product experts on how to accelerate your high-performance computing SoC designs. Find out about the latest market trends that will help you make important design decisions. Learn how specific features of Synopsys’ IP enables you to achieve the required functionality for your chip and deliver competitive products to market faster. Register now to learn about:

  • High-performance computing market trends impacting SoC designs from a senior executives in the IP business unit
  • Use cases and optimized IP solutions for AI, hyperscale data center, and networking applications
  • Meeting your evolving high-performance computing design requirements with a comprehensive IP portfolio including USR/XSR &HBI die-to-die, DDR5, HBM2/2E, PCIe 5.0, & CXL

Agenda

  • Senior executive presentation (including Q&A)                10 minutes
  • Product expert presentation (including Q&A)                   40 minutes
  • Q&A                                                                                          10 minutes

Speakers

John Koeter, Sr. VP of Marketing and Strategy

Executive Speaker: All Three Webinars

John Koeter joined Synopsys in 1998 and is currently Senior Vice President of Marketing and Strategy for IP. Before coming to Synopsys, Mr. Koeter held marketing, engineering, and corporate application engineering positions with Texas Instruments and Advanced Micro Devices.

Manmeet Walia, Sr. Product Manager

Product Expert Speaker: The New Frontier of Die-to-Die Connectivity: What You Need to Know for Silicon Success

Manmeet Walia brings over 18 years of experience in product management and system engineering covering ASSP, ASIC, and IP products for broad range of applications. Manmeet holds a Master of Science degree in Electrical Engineering from University of Toledo, and an MBA from San Diego State University.

Graham Allan, Sr. Product Manager

Product Expert Speaker: Navigating Between DDR5, LPDDR5, and HBM2/2E IP to Meet Your Design Goals

Graham Allan brings over 25 years of experience in the memory industry. Graham has spoken at numerous industry conferences and is a significant contributor to the SDRAM, DDR and DDR2 JEDEC memory standards. He currently holds 25 issued patents in the area of memory design.

Gary Ruggles, Sr. Product Manager

Product Expert Speaker: Keys to Achieving Maximum Throughput and Lowest Latency for PCI Express 5.0 and CXL Designs

Gary Ruggles brings over 25 years of experience in electronics and integrated circuit design. Gary began his career as Assistant Professor of Electrical and Computer Engineering at North Carolina State University, where he taught courses in Solid State Physics and VLSI Processing.

Details

Date:
June 23
Time:
10:00 AM - 11:00 AM
Event Tags:
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Website:
https://readytalk.webcasts.com/starthere.jsp?ei=1322777&tp_key=12fafcf45f&sti=web