Array

Instance

Array
(
    [title] => Recent Forum Threads
    [title_url] => 
    [ignore_sticky] => 0
    [exclude_current] => 0
    [limit] => 10
    [sluglist] => ["jobs-dashboard"]
    [rw_opt] => Array
        (
            [widget_select] => 1
            [pageid_281769] => 1
            [pageid_281772] => 1
        )

    [display_widget_mobile] => 1
    [rw_opt_exclude] => Array
        (
            [pageid_274493] => 1
            [cpt_podcast] => 1
            [cpta_podcast] => 1
            [category_16613] => 1
            [category_16631] => 1
            [taxonomy_series] => 1
        )

    [node_id] => Array
        (
            [0] => 2
        )

)

Threads

MOS-AK Workshop (Santa Clara)

Name: MOS-AK Workshop (Santa Clara)
Start: 2019-12-11T00:00:00-08:00
End: 2019-12-11T23:59:59-08:00
Location: Silvaco

December 11, 2019

Important Dates:	Call for Papers – Oct. 2019 2nd Announcement – Nov. 2019 Final Workshop Program – Dec 2019 MOS-AK Workshop: Dec.11, 2019 in timeframe of IEDM and Q4 CMC Meetings
Paper	Submission deadline: Nov.25, 2019 (Monday)
Venue:	Silvaco 2811 Mission College Blvd., 6th Floor Santa Clara, California 95054
Online	Registration is open any related enquiries can be sent to registration@mos-ak.org

Synopsis:	HiTech forum to discuss the frontiers of electron device modeling with emphasis on simulation-aware compact/SPICE models and its Verilog-A standardization. MOS-AK Meetings are organized with aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/Spice modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD tool vendors. The topics cover all important aspects of compact model development, implementation, deployment and standardization within the main theme – frontiers of the compact modeling for nm-scale MEMS/NEMS designs, CMOS/SOI and HEMT IC simulation. The specific workshop goal will be to classify the most important directions for the future development of the electron device models, not limiting the discussion to compact models, but including physical, analytical and numerical models, to clearly identify areas that need further research and possible contact points between the different modeling domains. This workshop is designed for device process engineers (CMOS, SOI, BiCMOS, SiGe, GaN, InP) who are interested in device modeling; ICs designers (RF/Analog/Mixed-Signal/SoC/Bio/Med) and those starting in that area as well as device characterization, modeling and parameter extraction engineers. The content will be beneficial for anyone who needs to learn what is really behind the IC simulation in modern device models.
Topics:	to be covered include the following: Advances in semiconductor technologies and processing Compact Modeling (CM) of the electron devices Verilog-A language for CM standardization New CM techniques and extraction software Open Source FOSS TCAD/EDA modeling and simulation CM of passive, active, sensors and actuators Emerging Devices, CMOS and SOI-based memory cells Microwave, mmW, RF device modeling, high voltage device modeling Microsystems, SoC, IP modeling Device level modeling for Bio/Med applications Nanoscale semiconductor devices/circuits and its reliability/ageing Technology R&D, DFY, DFT and IC Designs Foundry/Fabless Interface Strategies
Speakers	Tenatiative List (tba) Zhiping Yu, Tsinghua University (CN)/Stanford (USA) Benjamin Iniguez, URV (SP) Mansun Chan, UST (HK) Shuang Cai, Keysight (USA) Peter Lee, Micron (JP), Si2 CMC Lining Zhang, PKUSZ (CN) Roberto S. Murphy, INAOE (MX); EDS DL Chika Tanaka, Kioxia Corporation (JP) Colin Shaw, Silvaco (USA) Wladek Grabinski, MOS-AK (EU); EDS DL
Online	Abstract Submission is open (any related enquiries can be sent to abstract@mos-ak.org)