Mentor IC Tech Day – Athens

Overview

Join this IC Technology Day and learn how Mentors innovative products and solutions help engineers conquer design challenges in the increasingly complex worlds of board and chip design During this one-day Seminar split into three sessions, you will learn more about our solutions for chip design and verification.

Part 1 – Analogue IC Implementation – Tanner flow
The first part of the day will feature the ‘Tanner’ full-custom analog IC design suite from Mentor. Here, you will receive an overview presentation of the solution and live demo that will cover the main features of the schematic editor (S-Edit), layout editor (L-Edit), and how these tools enable an end-to-end design flow with industry-leading Mentor tools, such as simulation with AFS and physical verification with Calibre.

Part 2 – Solutions for AMS circuit verification challenges, targeted for analog and mixed signals design and verification engineers.
Mission-critical applications such as autonomous driving are forcing fundamental changes in the way chips are designed and verified. Most existing methodologies fall short when it comes to accuracy and coverage requirements, leading to over-margining, suboptimal power, performance and area metrics, yield challenges, and silicon failures. However, advancements in machine learning methods have resulted in disruptive improvements in this field, allowing orders of magnitude higher accuracy and coverage than what was previously achievable, with the same compute resources and runtime.

In the second session, we will go through the most common challenges posed by A/MS simulation and we will introduce Mentor solutions to tackle those challenges. The emphasis will be on Analog and Mixed-Signal verification, with an introduction on machine-learning algorithms and how they allow to efficiently simulate high yield (6-7 sigma) and obtain full corner characterization.

Part 3 – Calibre technical session, aimed to layout and circuit verification engineers.
Technology shrink in advance nodes required increasing of Design Rules. Those rules are much more complicated to check and code with verification tools. Calibre comes with a solution that will allow this verification.

Calibre leads the market for many years with innovative features, which ensures you can complete your layout design verifications, quickly and efficiently, all the major players in this arena use Calibre for their very advance node Design Rule Check development. The Calibre platform offers a unique combination of performance, accuracy, and integrated scripting environment allowing users to suit the specific and evolving needs of their circuit verification strategies.

During the last part of the day, we will offer a complete overview and update on circuit and physical verification techniques for mature and advanced technology nodes using Mentor Calibre solution.  We will also give an update on foundry qualified DK availability and license requirements

What You Will Learn

• Machine learning trends and applications
• Variation-aware design and verification with Solido Variation Designer
• Library characterization and validation with Solido ML Characterization Suite
• Mentor’s New Mixed-Signal Verification Platform Symphony – powered by AFS
• Case studies on methodology, results, and best practices
• Mentor Calibre complete platform for Circuit and Physical verification and advanced verification flow including reliability and design for manufacturability
• Mentor Calibre foundry design kits availability across multiple technology nodes

Who Should Attend

• Chief Operation Officer
• Technical Directors
• Design Managers
• Analog, Digital, RF and Mixed-Signal designers
• ASIC & FPGA Design and Verification managers
• Library design and characterization teams
• Digital implementation teams interested in library characterization and validation
• Analog, RF and Mixed-Signal verification engineers
• Layout and circuit verification engineers