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Mentor Forum for Calibre 2019 India
June 20 @ 9:00 am - 5:30 pm
Register For This Seminar
9:00 AM – 5:30 PM IST
Come to the Mentor Forum to learn from your fellow designers and from Mentor how to leverage your Calibre Platform to address all your verification needs, regardless of which markets your company is focused on.
The forum will focus on ‘Reducing Turnaround Time to design Smarter Innovations without compromising Accuracy’ with Mentor, a Siemens Business’.
To enable our customers to deliver smarter innovations to market faster, Mentor, a Siemens business is actively delivering new solutions and use models that enable our customers to more readily develop AI-powered technologies. We are also integrating advanced machine learning algorithms into our tools to enable those tools to deliver better results faster. Come hear experts from Mentor’s IC Calibre solutions portfolio describe what Mentor has to help customers deliver smarter IC innovations to market faster.
This event also brings you an opportunity to learn from Industry experts from Mentor – A Siemens Business on how to leverage the superior performance and capacity of the Calibre design-to-silicon (D2S) platform, known for delivering best-in-class performance, accuracy, and reliability. As technology shrinks to single digit nodes, design increases further in complexity and turnaround time becomes more and more critical. This forum will present you with the latest features implemented in Calibre, allowing you to fasten convergence to clean design and optimize the quality of your designs for higher performance and reliability. We will discuss as well the methods and utilities to help you reach the final Calibre quality signoff with best in class turnaround time.
Seating is VERY limited IN ORDER to maximize your learning experience, submit your REGISTRATION immediately to request your spot
What You Will Learn
- Addressing advanced circuit verification needs for ESD, EOS, signals crossing multiple power domains, advanced ERC and other reliability concerns at advanced and legacy nodes
- Yield analysis and critical feature identification capabilities, as well as layout enhancements, and printability and performance validation at advanced nodes
- Advanced design density analysis with multiple fill solutions to supply the optimum fill strategy for correct-by-construction results in both digital and custom/analog designs
- On-demand Calibre signoff design rule checking (DRC) for Custom and Digital design flows
- Improve Turnaround Time in Chip finishing activities by rapidly loading, displaying and saving large GDSII and OASIS® files.
- High performance parasitic extraction for digital, custom, analog and RF designs.
Who Should Attend
- Design Engineers
- Design Managers
- All IC Design Engineers who run Physical Verification or work on any part of Physical Design Flow.
- PDK Engineers who develop or maintain Physical Verification Rule Decks.
- CAD teams who create CAD flow for the design community and evaluate Design-to-Silicon tools.
Michael Buehler-Garcia manages all aspects of product management for Calibre Design product offerings, including product definition and launch, strategic positioning, ecosystem partnerships, and integration to all EDA flows both within Mentor and other 3rd party solutions. Michael came to Mentor in 2008 as part of the acquisition of Ponte Solutions, a DFM product provider. Prior to Ponte Solutions, he held senior executive positions at iRoC Technologies, PDF Solutions, and at Chartered Semiconductor (now GLOBALFOUNDRIES), along with Cadence Design Systems. Michael started his career at Motorola, holding technical positions in both the Government Electronics Group and the ASIC Semiconductor Division. He holds a BS in Mechanical Engineering and Alternate Energy Systems from Arizona State University.
08:30 AM – 09:00 AM Registration
09:00 AM – 09:10 AM Welcome | Mentor – A Siemens Business
09:10 AM – 09:20 AM Tech Talk – Ruchir Dixit, Mentor – A Siemens Business
09:20 AM – 09:50 AM Industry Keynote
09:50 AM – 10:20 AM Keynote | Michael Buehler, Mentor – A Siemens Business
10:20 AM – 10:30 AM Technical Keynote – Vikas
10:30 AM – 10:45 AM Coffee/Tea Break
10:45 AM – 11:30 AM Technical session | Accelrating PV Closure during DESIGN Creation Stage using Calibre RealTime – TBD
11:30 AM – 12:15 PM Technical session | Improve Design Efficiency using Calibre Power Via and Advacend Fill Flows – Fady Fouad
12:15 PM – 01:05 PM Lunch
01:05 PM – 01:50 PM Technical session | Address Complex Design Reliabilty Requirements using Calibre PERC – Hossam Sarhan
01:50 PM – 02:35 PM Technical session | Speeding DRC at early design stage using Calibre Advanced Solutions – Nermeen/Omaar
02:35 PM – 02:50 PM Coffee/Tea Break
02:50 PM – 03:35 PM Technical session | Advanced Chip Finishing and 3D-IC Solutions – TBD
03:35 PM – 04:20 PM Technical session | Achieve Accuracy and Performance during Parasitic Extraction using Calibre Solutions – Yousry ElMaghrby/Aya
04:20 PM – 04:50 PM Panel Discussion |
04:50 PM – 05:00 PM Wrap up & Closing