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Make in India – Employ Tanner AMS on your design for the SCL 180 nm PDK

September 4, 2019

Register For This Web Seminar

Online – Sep 4, 2019 
11:00 – 12:00 IST


This Webinar will feature experts from Mentor Graphics’ Tanner Product Division in the field of Custom and Analog IC design, covering the various capabilities in the Tanner AMS tool.  After a quick overview of the various tool capabilities, a design mapped to Semi Conductor Lab (SCL) 180 nm PDK will be pushed through the Tanner Analog/Mixed Signal flows.

Being the tool of choice at 1000’s of customer places, the Tanner AMS product is tightly integrated with the rest of Mentor Eco System (AFS, Eldo, T-Spice, ModelSim/Questa on the simulator front, Calibre on the Physical Verification front and Nitro/Oasys on Digital Implementation front)

What You Will Learn

Learn about the Tanner EDA design flow and see some of the capabilities we’ve added now that we’re part of the Mentor family.  Topics will include Analog design and simulation, mixed signal design and implementation, physical verification and Tanner Digital Implementation for digital blocks

Demo of Tanner Analog Mixed Signal Tools and Tanner Digital Implementer (TDI) using SCL 180 nm PDK

Who Should Attend

  • Analog Design Engineer
  • Analog Design Manager
  • Digital Designer (of Big Analog-Small Digital blocks)
Murali Seshadri

Murali SeshadriMurali Seshadri works as a Sr. Product Manager with the Tanner product division of Mentor Graphics and is based at their Bangalore office. Murali is currently responsible for Technical Marketing and evangelization of the Tanner solutions in Indian Market both for short term as well long term proliferation. He enjoys working with customers (primarily startups) to support their evolving needs. Murali has over 20+ years of experience in the Semiconductor industry and has previously worked for companies Synopsys, Cypress Semiconductor, Intel and Qualcomm in various roles ranging from CAD Engineer, Applications Engineer, Design Engineer, Design Manager and Product Engineer. He was part of the team that developed the worlds’ first 45 nm commercial chip at Intel. Murali received his Bachelors of Science Degree in Electronics & Communication from University of Madras and Masters’ degree in Electrical Engineering from University of Kentucky, Lexington in the USA

Dr. Suvradip Ghosh

Dr. Suvradip GhoshDr. Suvradip Ghosh brings in 10+ years of experience in the Analog design space. His’ areas of interest include Device characterization, schematic & layout, & Circuit Simulation. Barani currently works as an Application Engineer for the Tanner product of Mentor Graphics in Bangalore. Before joining Mentor Graphics, Barani worked at Entuple Technologies Pvt. Ltd in their EPiCS team and led an AE team supporting sales efforts presenting EDA products, technical workshops, seminars, & key customer engagements. Prior to Entuple, Barani was a Branch/Tech Manager & Sr. AE, for Trident Techlabs, representing the IC & PCB Design tools – including Tanner, Calibre, Questa/ModelSim, Eldo, & many others. Barani holds a Diploma in Electronics from NTTF Electronics TC & a PG Diploma in VLSI from Sandeepani – School of VLSI Design, both in Bangalore, India

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