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IP-SoC (France)

December 3 @ 8:00 am - December 4 @ 5:00 pm

Euro250
IP-SoC 2019

IP-SoC 2019 will be the 22nd edition of the working conference fully dedicated to IP (Silicon Intellectual Property) and IP based electronic systems.

The event is the annual meeting for IP providers and IP consumers to share information about technology trends, innovative IP SoC products, Breaking IP/SoC News, Market evolution and more.

Meet the gurus in the field and Get the best vision to orientate your business.

And in addition you cannot miss the most friendly IP SoC community meeting while enjoying like each year French Wine Contest followed by a “French Touch” banquet.

Click here to register >>

Tentative Program

Day 1: Executive day

8:40 am Welcome

Gabrièle Saucier
CEO
Design & Reuse

 From Technology to IP
9:00 am Impact of the SOI technology and its European Ecosystem on the upcoming 5G technology wave

Francois Brunier
Partnership Program Manager
Soitec

9:20 am Acceleration and Differentiation for a world of a trillion devices

Mike Eftimakis
Director of Business Innovation Strategy
Arm

9:40 am IP Status 2010-2019 – What’s next for 2020-2030?

Eric Esteve
IPnest-Semiwiki

10:00 am RISC-V Helps Getting Your Chip Popular

Frankwell Lin
President
Andes Technology Corp.

10:20 am  Break
 IP sharing and worldwide dissemination
10:40 am Integrated Circuit IP Sharing Platform – Focus on IP Services to Help Design Innovation

Weihua Xin
Director
IMECAS

11:00 am Gaps and SOC consumer pain points

Mukund Pai
SoC Power Lead
Intel Corporation

11:20 am IP dissemination: what are the bottleneck and the solution ?

Gabrièle Saucier
CEO
Design & Reuse

11:40 am Panel : Worldwide IP Dissemination :How to improve the relation between IP Providers and IP Consumers over continent?
With the participation of : Shanghai Jiatao Industrial Co., ltd., Intel Corporation, STMicroelectronics, …
12:40 pm  Lunch Break
 Automotive and High safety systems
2:00 pm Automotive-Qualified IP for Evolving Integrated ADAS Domain Controller SoCs

Ramin Navai
FAE for DesignWare Interface IP
Synopsys, Inc.

2:20 pm Autonomous Vehicle: From chip to systems design verification continuity

Gabriele Pulini
Product Marketing Manager
Mentor, a Siemens Business

2:40 pm Testability Challenge of safe-critical real-time systems

Oussama Abassi
Hardware Engineer
Safe Connect Systems

3:00 pm  Break
 Security Solutions
3:30 pm Why should your next secure design be PUF based

Vincent TELANDRO
Sales Manager
Thales DIS Design Services SAS

3:50 pm FPGA-based Hardware Security Module

Pieter Willems
Director Sales and Marketing
Silex Insight

4:10 pm Secure networking in an unsafe environment

Gijs Willemse
VP, Silicon IP and Secure Protocols, Products and Engineering
Verimatrix

4:30 pm Securing IoT with a hardware Secure Element

Marc Renaudin
CTO
Tiempo SAS

4:50 pm  Break
 Innovative solutions
5:20 pm A Novel Event Based Image Sensor Architecture

Mohamed Akrarai
Phd student
TIMA Laboratory

5:40 pm A High Performance Cache Coherent Interconnect for Multi-core Processors

Jose Simon
Principal Engineer
CDAC

6:00 pm Embracing High Speed, Low Power, Complex Security Analytics at the Heart of the Cloud

Sakir Sezer
CTO
Titan IC

6:20 pm  Break
7:00 pm  French Wine tasting Contest
7:45 pm  Banquet

Day 2: Designer Day

 Introduction
9:00 am Innovation starts here! Low-cost access to the world’s best SoC portfolio

Mike Eftimakis
Director of Business Innovation Strategy at Arm
Arm

9:20 am Benefits of IP-XACT for IP Providers: Highly configurable IP study case with interconnect IP.

Vincent Thibaut
Chief Strategic Officer
Magillem

9:40 am How to Identify and Minimize IP Security Risks – IP Security Assurance Standard

Ireneusz Sobanski
Senior Validation Engineer
Intel Corporation

10:00 am Panel : Is the New emerging standard IP Security Assurance (IPSA from Accelera working group) the solution?
In recent years, many hardware security weaknesses arising from integrated circuit hardware vulnerabilities have been exposed. These include lack of virtual machine isolation, secure credential leaks, and privilege escalation. These have put hardware design in the spotlight and raised questions about IC security.

  • How is security addressed over the hardware development lifecycle today?
  • How should we assess and mitigate security risk in IC design going forward?
  • Do we have adequate methodologies, procedures and technology to address it?

With the participation of : Intel Corporation, SiFive, Inc., Synopsys, Inc., …

11:00 am  Break
 Power Optimization
11:20 am Power/Performance tradeoffs and its criticality for today’s SOCs

Mukund Pai
SoC Power Lead
Intel Corporation

11:40 am Simplify Energy Efficient designs with cost-effective SoC Platform

Pierre Gazull
Business Development and Marketing Manager
Dolphin Design SAS

 Analog Design and IP migration
12:00 pm Bluetooth IP Migration – Leveraging FDSOI Back Gate Biasing feature

Sowmyan Rajagopalan
CTO
Thalia Design Automation

12:20 pm Optimize the Silicon Process Porting of Physical IP

Tony Stansfield
Chief Technical Officer
sureCore, Ltd.

12:40 pm Analog Design Automation: a new approach to Analog IP

Mike Hulse
CTO
Agile Analog

1:00 pm  Lunch Break
 IP-SoC integration
1:40 pm RDC sign-off for IP integration in modern SoC designs

Johannes Biedermann
Senior FAE
Frelance Engineer, representing Real Intent Europe

2:00 pm SoC Architecture: Ensuring IP Compatibilities across the SoC : Physical and Logical

Radhakrishna Moorthy Sadhu
SoC Architect, DMTS-Senior Member
Wipro Technologies

 Synchronization or asynchronous solutions
2:20 pm Desynchronizing Circuits Synthesized with CatapultC

Yoan Decoudu
PhD student
TIMA Laboratory

2:40 pm Deterministic & Precise Synchronization in sub-microsecond range using EtherFly modular IPs infrastructure

Maxime Apollonio
Digital electronic Engineer
SCS Safe Connect Systems SAS

3:00 pm  Break
 Verification & prototyping
3:20 pm Open Source Virtual Platforms for SW Prototyping on FPGA based HW

Mark Burton
Founder
GreenSocs

3:40 pm Compiler Verification, More Necessary Than Ever!

Marcel Beemster
CTO
Solid Sands B.V.

4:00 pm  Conclusion and Giveaway.

Details

Start:
December 3 @ 8:00 am
End:
December 4 @ 5:00 pm
Cost:
Euro250
Website:
https://www.design-reuse.com/ipsoc2019/registration/

Organizer

Design and Reuse S.A.

Venue

Design and Reuse S.A.
12 rue Ampere
Grenobe, 38 000 France
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Phone:
+33 476 21 31 02