IP Integration Challenges of Complex SoC Platforms

The explosion of AI and pervasive intelligence has created an exponential demand for increasing compute power, best addressed using GPUs (Graphics Processing Unit) and FPGAs (Field Programmable Gate Arrays). This is accomplished by providing a HW platform that runs computationally intensive machine learning algorithms fast and efficiently. That said, both GPU and FPGA vendors have aggressively improved their performance on AI applications. However, the design of GPU and FPGA brings its own challenges. Such challenges include mixing a variety of proprietary and 3rd party IP built from varying layout styles (custom, P&R) and carrying out varying functions (SerDes, RF ADC/DAC, HBM, CPU) with varying layout formats (gds, oasis). Further, there are challenges with IP consistency and re-use, different hierarchies sharing IP sub-blocks, preserving golden IP, etc. This webinar covers those challenges to illustrate a methodology that offers optimal productivity and performance.

PRESENTED BY
An-Jui Shey is a senior application engineer of Empyrean Software. He is responsible for customer
support of design tools and methodologies for SoC design. Shey has extensive experience and expertise
in tool automation and design methodology development. Shey received a Ph.D. degree in electrical
engineering from University of California, San Diego.