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Interfacing DDR with Programmable Logic on the Xilinx Versal NoC – Webinar

May 20 @ 2:00 PM - 2:30 PM

Free

Join us as one of our top engineers talks about interfacing DDR with programmable logic on the AMD – Xilinx Versal NoC. The webinar will include a live demo and Q&A session.

This session will be 30 minutes.

 

BLT (Bottom Line Technologies) is an engineering company that provides custom electronic solutions for commercial and GOV/IC/AERO applications. We have been designing FPGAs / SoCs and custom chips, embedded software, circuit boards and complete systems for over 30 years. BLT is also a Xilinx Authorized Training Provider.

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Details

Date:
May 20
Time:
2:00 PM - 2:30 PM
Cost:
Free
Event Categories:
,

Organizer

BLT – Bottom Line Technologies
Phone:
888-945-4691
Email:
info@bltinc.com
View Organizer Website

Venue

Online