Increase Your Debug Efficiency Using a Modern Debug Environment

Overview

Complex testing and methodology with complex silicon require powerful but simple to use debug solutions. The Visualizer Debug Environment provides a common debug solution for simulation, emulation and other engines, including Verilog, VHDL, UVM, SystemC, C/C++, Assertions and Coverage.

This session will introduce the Visualizer Debug Environment for VHDL.

What You Will Learn

• Post-simulation and live-simulation debug
• Driver tracing and X-tracing
• Source code debug
• Waveform debug

Who Should Attend

• Verification engineers and managers
• FPGA Design and Verification Engineers