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Increase Your Debug Efficiency Using a Modern Debug Environment
June 3, 2020 @ 2:00 PM - 3:00 PM
Register For This Web Seminar
14:00 – 15:00 Europe/Berlin
Complex testing and methodology with complex silicon require powerful but simple to use debug solutions. The Visualizer Debug Environment provides a common debug solution for simulation, emulation and other engines, including Verilog, VHDL, UVM, SystemC, C/C++, Assertions and Coverage.
This session will introduce the Visualizer Debug Environment for VHDL.
What You Will Learn
- Post-simulation and live-simulation debug
- Driver tracing and X-tracing
- Source code debug
- Waveform debug
Dirk HansenApplication Engineer – Digital Design & Verification at Mentor, a Siemens Business
Who Should Attend
- Verification engineers and managers
- FPGA Design and Verification Engineers