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Improve your Debug Productivity
With today’s more complex designs, we tend to see a growing productivity gap between design and verification, so we need to maximize the reusability of your verification environment, improve the automation, raise the level of abstraction… but we need higher performance, context-aware debug supporting the complete logic verification flow
During this session, we will cover different techniques for debugging your RTL
Source code while running a live simulation
What You Will Learn:
- How to debug complex and mixed verification environments
- How to use a set of synchronized views for analyzing waveforms and source code
- How to find (X values) and trace an event back in time
- How to explore the physical connectivity of your design
Meet the speakers
As part of CADlog team, he is dedicated to deliver productive engineering and HDL development solutions to customers via the best in class software and support for tomorrows complex designs.