IC Packaging Technology Course

Integrated Circuit packaging has always been integral to IC performance and functionality. This two-day class will detail the vital technologies required to construct IC packages in a reliable, cost effective, and quick time to market fashion. An emphasis will be given to manufacturing, processes and materials selection tailoring and development. Each fundamental package family will be discussed, including flip chip area array technologies, Wafer Level Packaging (WLP), Fan-Out Wafer Level Packaging (FO-WLP), and the latest Through Silicon Via (TSV) developments. Additionally, future directions for each package technology will be highlighted, along with challenges that must be surmounted to succeed.

Visit Semitracks | Semiconductor and Electronics Training to sign up and get early bird pricing!