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How to Build PCIe Speed Adapters for In-Circuit SoC Emulation

October 22, 2020 @ 11:00 AM - 12:00 PM


Hardware assisted verification became much more affordable due to the availability of high capacity FPGAs such as Xilinx Virtex UltraScale US440 and their adoption for emulation verification environments. One of the advantages of FPGA-based emulation systems is that it’s much more flexible than traditional processor-based systems when it comes to connecting external peripherals. In this presentation we will demonstrate how to take advantage of the FPGA platform to build the PCI Express speed adapter and connect the emulated SoC design with the external PCIe-based Network Interface Card that runs at its target speed and provides connection of the SoC to the real LAN network traffic.








  • In-Circuit Emulation with Speed Adapters
  • Designing Speed Adapters with PCIe
  • PCIe demo with speed adapter
  • Setup and Debugging with HES-DVM
  • Q&A

Presenter Bio:

Chris joined Aldec in 2001 and was a key member of the team that developed HES-DVM™, Aldec’s FPGA-based emulation and prototyping technology. In his engineering career he has also worked in the fields of HDL design verification, testbench automation and DO-254 compliance. Krzysztof has practical experience and a deep understanding of hardware assisted verification methodologies. Krzysztof graduated as M.Eng. in Electronic Engineering (EE) at the AGH University of Science and Technology in Krakow, Poland.

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October 22, 2020
11:00 AM - 12:00 PM
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