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HLS Design and Verification Seminar 2023
December 1 @ 1:00 PM - 4:00 PM
We will be holding a high-level synthesis technical forum. The past few years have been held online, but this year we were able to return to the venue. We have prepared a variety of proposals, including success stories and new technology updates related to high-level design and verification, so please come and join us, even if you are busy. We look forward to seeing you there.
Date: Friday, December 1, 2023, 13:00-16:00 (Registration starts: 12:30)
Japan Cadence Design Systems
Innotek Co., Ltd. IC Solution Headquarters
Sponsored by: MathWorks Japan
Innotek Building 2nd floor Seminar Room
Registration deadline: November 30th (Thursday) 17:00
(* Registration will close once capacity is reached)
Contact: Cadence Japan CadenceCONNET Secretariat email@example.com