HiPChips Conference

Machine learning (ML), high performance computing (HPC), and the convergence of both are becoming the major driving force to define future computer architectures in both data center and edge. As performance requirements of workloads have catapulted, heterogeneous computing with domain-specific accelerators (DSA) is deemed as a new computing paradigm to meet the computation demand in the post-Moore era.

While an accelerator architecture is still evolving to continuously integrate more components to boost its computing horsepower, the increasing cost of silicon results in the rise of chiplet architectures.

As a promising alternative to advance a chip design, chiplets take advantages of the recent development of packaging technologies to reduce the complexity of traditional monolithic system-on-a-chip (SoC) design by improving system-level interconnection density and reducing power consumption via mix-and-matching existing or new components and integrating them into a single package. The modularized approach presumably can shorten the development time and improve yield to lower the manufacturing costs. However, one of the biggest challenges industry currently faces is lack of standards and tools to allow different pieces of silicon across vendors to be tied together and work seamlessly through a common interface.

At the same time, as individual devices continue to shrink and more heterogeneous chiplets are integrated, innovations on chiplet-based computing architectures will be required. Though communication between chiplets is typically slower than on-chip communication, distances are shorter and there might be more conduits for inter -chip signals.Thus, collectively inter-chiplet communication may be faster with less energy consumption. So how to distribute data among chiplets and optimize data movement for efficient spatial parallel processing is another key to success.

The Open Compute Project Foundation (OCP) is a global industrial consortium with the mission to enable mainstream delivery of open and efficient designs for scalable computing. Its Open Domain-Specific Architecture (ODSA) working group was incubated to define the standards for a coherent cross-industry open ecosystem of chiplets and make a viable chiplet market a reality. ODSA is situated strategically to address challenges of chiplet interoperability due to inherent limitations of proprietary designs, including physical interfaces, chiplet base functionalities for top software stack, as well as packaging and testing of products across vendors.

ODSA’s goal is to create an open chiplet marketplace that allows systems in packages to be built from building blocks from multiple vendors with speed and simplicity to enable shipping new solutions faster. To achieve this, ODSA strategy is centered on following three core areas:

Area 1: Enable open die to die interfaces to reduce barrier for interoperation

Area 2: Create reference designs as starting points for allowing technology development

Area 3: Define business reference workflows for enabling reusable, open practices

The 1st International workshop on the High Performance Chiplet and Interconnect Architectures (HiPChips-2022), endorsed by OCP/ODSA working group, is a new workshop targeting on researches with an interpenetration effect between academia and industry: on one hand, this workshop helps researchers understand the latest progress on chiplet-powered architectures for data-intensive applications and ML/HPC-motivated chiplet designs; on the other hand, it helps promote the open chiplet standards to foster collaborations on further development of the chiplet ecosystem. The major objective of this workshop is to bring researchers from academia and industry together to communicate their ideas, share knowledge of advanced technologies and new development on but not limited to the following topics:

• Chiplet-based accelerator level parallelism (ALP)
• Chiplet architecture for large scale system design
• Physical and logical inter-die interface design for heterogeneous architectures
• Coherent and non-coherent data sharing protocols via fast chiplet interconnection
• Chiplet architectures for in-memory computing and other emerging technologies
• ODSA-based 3D architecture for efficient ML acceleration
• Chiplet-based secure computing
• Power evaluation and performance modeling of chiplet architecture
• Software optimization framework with fast inter-chiplet network
• Chiplet topology aware ML optimizations