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Hierarchical PI Analysis of Large Designs with Voltus Solution

March 11

Hierarchical PI Analysis of Large Designs with Voltus Solution

Memory requirements and runtime for full chip EMIR analysis has become a major challenge at advanced nodes as it is not uncommon to see designs with 100s of millions of cells and some even in the multi-billion range. To run a flat analysis requires multiple terabytes of memory over a distributed network. To mitigate these issues, Voltus enables designers to run hierarchical analysis using Voltus-XM (Extreme Modeling) technology. Voltus-XM lets designers create xPGV models for their IP blocks which accurately capture the demand current and electrical parasitics of the block. These xPGV models are an order of magnitude smaller compared to the fully extracted block and when used in the chip level analysis, it can help significantly reduce runtime and memory. The modeling methodology used in Voltus-XM ensures minimal result difference relative to a fully flat analysis. This webinar will cover generation of xPGV models and their use in the IC-level analysis including package model.

Key Take-aways:

  • Run your largest designs much faster with lower memory
  • Very accurate sub-chip analysis including impact of chip-level demand current and parasitics
  • Reuse IP models in different designs or for multiple instantiations within a design

Date and Time

Tuesday, March 11, 2021
Time: 9:00-10:00am  (PST)

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