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Gain a Design-to-revenue Edge in FPGA and SoC Designs with a Full Deployment of Clock-Domain Crossing Analyses and Verification
June 27 @ 8:00 am - 9:00 am
Today’s complex, multi-clock designs create challenges that must be addressed to avoid costly re-spins and long debug cycles. Design analysis and verification technologies that focus specifically on Clock-Domain Crossing (CDC) issues, using an integrated combination of verification technologies, have become a requirement. Design reviews and stringent methodologies are no longer enough. This web seminar explains the importance of a complete CDC methodology to produce error-free silicon.
What You Will Learn
- The 3 common areas where CDC paths have functional errors
- How Questa CDC products can identify and eliminate all 3 common CDC error types
- Methods for effective CDC verification
Who Should Attend
- ASIC/IC and FPGA Design and Verification Engineers, Project Leads, and Managers