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FPGA Platform Design & Verification Seminar Series 2019
June 26, 2019 @ 10:00 AM - 3:30 PM
Please join us for a free FPGA Platform Design and Verification seminar. If you are a verification engineer, design engineer, system architect or design manager focusing on FPGA projects, you won’t want to miss this event.
- June 26, 2019
- Schaumburg, IL
Attendees of this seminar will learn about the Synopsys FPGA Platform to help find and fix bugs faster. The FPGA Platform provides an end-to-end flow, combining accelerated simulation and debug, clock domain crossing, RTL analysis, and the highest performance synthesis.
Agenda Topics
10:00 a.m – 03:30 p.m.
(Lunch provided)
- FPGA Platform overview – Find and fix bugs faster!
- Simulation, debug and the benefits of UVM adoption
- Clock domain crossing and linting overview
- Synthesis and design challenges for high reliability
- Guest speaker – Discussing FPGAs
- Demonstration of the Synopsys FPGA Platform in action
*Agenda subject to change
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