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Formal verification to improve design quality and accelerate time to market

September 8

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Register For This Web Seminar

Japan-2020/09/08
2 :00-3 :30 JST

Overview

In order to verify that electronic systems are becoming more complex and that they work properly, you can’t get the job done without a personalized suite of verification tools that can keep up with the needs of relentless growth.

This webinar is the fourth in a series of Mentor Functional Verification Solutions-Latest Updates-Summer 2020 series. Functional verification always requires multi-faceted problem solving, and this webinar series gives an overview of Mentor’s functional verification tools that provide high productivity in all aspects. Here’s how each tool is optimized to find bugs and close coverage, as early as possible in the development process.

Formal verification to improve design quality and accelerate time to market: Formal automated app

Many critical verification tasks, such as dynamic connectivity verification, register policy verification, and critical signal path and register biosynthesis verification, require weeks or more of testbench development and execution, yet unexpected bugs It is difficult to identify all. In contrast, an “app” that automates formal verification can comprehensively verify important verification items without having to be familiar with the formal verification mechanism. Questa Formal introduced in this session provides various applications that can be applied from the initial design stage.

Content

  • Eliminating deadlocks in complex logic
  • Accelerate code coverage closure
  • Identifying register policy corner cases
  • Automatic check for conditional and sequential connections
  • Unintentional security backdoor discovery
  • Root cause analysis of “X” propagation immediately after resetting at low power
  • Verification of clock gate and SEU mitigation circuit

Formal verification to improve design quality and accelerate time to market: Formal property checking

Not even a constrained random test can search the entire state space of a design. In addition, in simulation, it may take several weeks to create a test bench, which may reduce the time from bug discovery to bug fix. In this session, we will introduce high-value verification using formal property checks and methods to thoroughly eliminate design errors that may occur.

Content

  • Formal analysis mechanism and proof for all inputs/total time
  • Create effective formal test benches with simple basic properties
  • Introducing methodologies such as bug hunting, providing full legitimacy of DUT functionality, deadlock free, etc.

 

ABOUT PRESENTERS
Mark Esslinger
Mark EsslingerMark Esslinger has over 20 years of experience in chip design and verification, pre/post sales support and technical marketing. As a Technical Marketing Specialist in the Design Verification Technology Division of Mentor, a Siemens Business, he specializes in assertion-based methods and formal verification, helping clients around the world adopt advanced methodologies. Prior to joining Mentor, he worked in engineering and technical marketing organizations in the semiconductor, systems and EDA industries such as Lockheed, Synopsys, Abstract, Sente/Sequence, Averant and AccelChip. Obtained MSEE from Santa Clara University.

Joe hapsy
Joe hapsyJoe Hapsey III is based in the Mentor office in Silicon Valley, California, as part of the Product Management team in the Design Verification Technology Division of Mentor, a Siemens Business. He is responsible for the Questa Formal product line of automation applications and advanced property checking. Prior to joining Mentor, he was responsible for product management and marketing of products covering various aspects of hardware and software functional verification at several EDA companies. Prior to marketing, he worked as an electrical engineer in FPGA design, EDA tools for FPGAs and ASICs, and ASIC verification. He has BSEE, MSEE and MBA degrees from Cornell University in Ithaca, NY.

Target students

  • Hardware designer
  • Development project leader
  • Verification engineer
  • Development environment supporter